Techniques for duty cycle correction

A method comprising:

• measuring a duty cycle generated by a target clock via use of a sample clock, the duty cycle to be measured based on a periodic sampling of the target clock that samples the target clock at a rate that is greater than 1 prime number ratio of a reference clock cycle time, wherein the reference clock cycle time is to set a measurement cycle time over which the duty cycle is to be measured;
• determining a duty cycle error based on the periodic sampling of the target clock during the measurement cycle time;
• and
• adjusting the duty cycle generated by the target clock based, at least in part, on the duty cycle error.

A memory controller comprising:

• input/output interface circuitry arranged to couple with a memory device;
• and
• duty cycle correction circuitry to:
• measure a duty cycle generated by a target clock via use of a sample clock, the duty cycle to be measured based on a periodic sampling of the target clock that samples the target clock at a rate that is greater than 1 prime number ratio of a reference clock cycle time, wherein the reference clock cycle time is to set a measurement cycle time over which the duty cycle is to be measured;
• determine a duty cycle error based on the periodic sampling of the target clock during the measurement cycle time;
• and
• adjust the duty cycle generated by the target clock based, at least in part, on the duty cycle error.