Dynamic random access memory applied to an embedded display port

A dynamic random access memory (DRAM), comprising:

• a DRAM core cell comprised in the DRAM, wherein the DRAM core cell is supplied with a first voltage within a first voltage range to make the DRAM core cell operate at the first voltage, and the DRAM core cell is a volatile memory cell, wherein the first voltage is lower than 1.1V;
• and
• an input/output circuit comprised in the DRAM, wherein the input/output circuit is electrically connected to the DRAM core cell, and the input/output circuit is supplied with a third voltage to make the input/output circuit operate at the third voltage, wherein the third voltage is lower than 1.1V;
• wherein the DRAM core cell and the input/output circuit are formed on a single chip, the input/output circuit is external to the DRAM core cell, and the first voltage is greater than the third voltage.

A dynamic random access memory (DRAM), comprising:

• a DRAM core cell comprised in the DRAM, wherein the DRAM core cell is supplied with a first voltage to make the DRAM core cell operate at the first voltage, and the DRAM core cell is a volatile memory cell;
• and
• an input/output circuit comprised in the DRAM, wherein the input/output circuit is electrically connected to the DRAM core cell, and the input/output circuit is supplied with a third voltage to make the input/output circuit operate at the third voltage, wherein the third voltage is lower than 1.1V;
• wherein the first voltage is greater than the third voltage, and the DRAM is capable to be applied to an embedded display port (eDP).