Fully differential amplifier

A fully differential amplifier comprising:

• a first amplifying circuit configured to receive a first input voltage signal and provide first output voltage signal;
• a second amplifying circuit configured to receive a second input voltage signal and to provide second output voltage signal;
• a third amplifying circuit configured to receive configured to receive the first input voltage signal and provide a third output voltage signal;
• a fourth amplifying circuit configured to receive the second input voltage signal and provide fourth output voltage signal;
• a common gain setting network including a plurality of resistors to receive an injection signal and configured to interface with the first amplifying circuit and the second amplifying circuit, and
• a summing network includes a plurality of resistors configured to:
• provide a first common mode component and a second common mode component;
• and
• provide a first compensation signal to an inverting input of the first amplifying circuit and a second compensation signal to an inverting input of the second amplifying circuit in response to receiving the third output voltage signal and the fourth output voltage signal to prevent the first common mode component from being present in the first output voltage signal and the second common mode component from being present in the second output voltage signal.

A fully differential amplifier comprising:

• a first amplifying circuit configured to receive a first input voltage signal and provide a first output voltage signal;
• a second amplifying circuit configured to receive a second input voltage signal and to provide a second output voltage signal;
• a summing circuit configured to provide a common mode component of the first input voltage signal and the second input voltage signal;
• a compensation circuit configured to amplify the common mode component of the first input voltage signal and the second input voltage signal and output an injection signal, and
• a common gain setting network including a plurality of resistors to receive the injection signal and configured to interface with the first amplifying circuit, the second amplifying circuit and the compensation circuit to prevent the common mode component from being present in the first output voltage signal and the second output voltage signal based at least on splitting the injection signal with the plurality of resistors to provide a first injection signal to the first amplifying circuit and to provide a second injection signal to the second amplifying circuit.