Plane level dedicated starting program voltage to reduce program time for multi-plane concurrent program operation

A controller in communication with a memory apparatus including memory cells connected to one of a plurality of word lines and disposed in memory holes and configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory holes organized in rows grouped in a plurality of strings, the plurality of strings comprise a plurality of blocks comprising a plurality of planes, the controller configured to:

• instruct the memory apparatus to program the memory cells connected to one of the plurality of word lines and associated with one of the plurality of strings in each of the plurality of planes and acquire a smart verify programming voltage individually for each of the plurality of planes in a smart verify operation including a plurality of smart verify loops;
• and
• instruct the memory apparatus to concurrently program at least some of the memory cells connected to each of the plurality of word lines in each of the plurality of planes in a program operation using the smart verify programming voltage individually acquired for each of the plurality of planes in the smart verify operation.

A method of operating a memory apparatus including memory cells connected to one of a plurality of word lines and disposed in memory holes and configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory holes organized in rows grouped in a plurality of strings, the plurality of strings comprise a plurality of blocks comprising a plurality of planes, the method comprising the steps of:

• programming the memory cells connected to one of the plurality of word lines and associated with one of the plurality of strings in each of the plurality of planes and acquiring a smart verify programming voltage individually for each of the plurality of planes in a smart verify operation including a plurality of smart verify loops;
• and
• concurrently programming at least some of the memory cells connected to each of the plurality of word lines in each of the plurality of planes in a program operation using the smart verify programming voltage individually acquired for each of the plurality of planes in the smart verify operation.