Equalizer circuit
AssigneeRohm Co., Ltd.
InventorShinichi SAITO
Life of this patent
Estimating the term…
Abstract
An equalizer circuit includes a variable gain equalizer circuit. A third transistor MN for gain adjustment is coupled between a source of a first transistor that constitutes an input differential pair of the variable gain equalizer circuit, and a first current source IB. A fourth transistor MN for gain adjustment is coupled between a source of a second transistor that constitutes the input differential pair, and a second current source IB. A first bias voltage Vb is supplied to the gates of the third transistor MN and the fourth transistor MN, so as to enable DC gain control of the variable gain equalizer circuit.
Claims10
An equalizer circuit comprising:
- a variable gain equalizer circuit;
- and
- a first bias circuit structured to generate a first bias voltage;
- the variable gain equalizer circuit comprising:
- a first input terminal;
- a second input terminal;
- a first transistor having a gate coupled to the first input terminal;
- a second transistor having a gate coupled to the second input terminal;
- a first resistor coupled to a drain of the first transistor;
- a second resistor coupled to a drain of the second transistor;
- a first current source;
- a second current source;
- a third transistor coupled between a source of the first transistor and the first current source, with a first bias voltage applied to the gate;
- a fourth transistor coupled between a source of the second transistor and the second current source, with the first bias voltage applied to the gate;
- a third resistor coupled between a connection node of the third transistor and the first current source, and a connection node of the fourth transistor and the second current source;
- and
- a capacitor coupled in parallel to the third resistor.
Dependencies are inferred from the claim text.