Method of manufacturing a semiconductor package and semiconductor package manufactured by the same

A method of manufacturing a semiconductor package, the method comprising:

• forming a two-level type multi-stack structure by stacking first and second semiconductor chips on a carrier substrate with an offset to expose chip pads of the first and second semiconductor chips;
• forming a reverse wire bond by bonding one end of a reverse wire to a chip pad of the first semiconductor chip and the other end of the reverse wire to a conductive bump on a chip pad of the second semiconductor chip;
• molding the two-level type multi-stack structure using a mold layer;
• and
• processing the two-level type multi-stack structure to expose the conductive bump and the other end of the reverse wire in the reverse wire bond through an upper surface of the mold layer.

A semiconductor package comprising:

• a multi-stack structure including at least two semiconductor chips stacked on a carrier substrate with an offset so that chip pads of the semiconductor chips are exposed;
• a mold layer configured to mold the multi-stack structure;
• a vertical wire having one end bonded to a chip pad of a second-highest semiconductor chip under an uppermost semiconductor chip of the at least two stacked semiconductor chips to form a vertical wire bond, the other end of the vertical wire extending through the mold layer to be exposed above an upper surface of the mold layer;
• and
• a conductive bump formed on a chip pad of the uppermost semiconductor chip, the conductive bump exposed through an upper surface of the mold layer.