Gate spacer in stacked gate-all-around (gaa) device architecture

An integrated circuit structure comprising:

• an upper device comprising an upper source region, an upper drain region, an upper body of semiconductor material laterally extending from the upper source region to the upper drain region, and an upper gate structure wrapping around at least a corresponding section of the upper body;
• a lower device comprising a lower source region, a lower drain region, a lower body of semiconductor material laterally extending from the lower source region to the lower drain region, and a lower gate structure wrapping around at least a corresponding section of the lower body;
• and
• a gate spacer structure including (i) an upper portion separating the upper gate structure from the upper source region, (ii) a lower portion separating the lower gate structure from the lower source region, and (iii) an intermediate portion between the upper and lower portions, the intermediate portion extending laterally within at least one of the upper and lower gate structures, or extending between the upper and lower gate structures.

An integrated circuit structure comprising:

• an upper source region, a lower source region below the upper source region, and an isolation region between the upper source region and the lower source region;
• and
• a spacer structure comprising dielectric material and having (i) an outer sidewall adjacent to the upper source region, the lower source region, and the isolation region, and (ii) an inner sidewall opposite the outer sidewall,
• wherein an entirety of the outer sidewall that is adjacent to the upper source region, the lower source region, and the isolation region is substantially coplanar, and
• wherein the inner sidewall has (i) a first section and (ii) a second section that is laterally offset from the first section by at least 1 nanometer (nm).