Semiconductor structure including barrier layer between electrode layer and underlying substrate

A semiconductor structure comprising:

• a substrate including circuitry therein;
• and
• a semiconductor stack on the substrate, the semiconductor stack including:
• a first electrically conductive layer including a metal and electrically coupled to the circuitry of the substrate;
• and
• a second electrically conductive layer between the substrate and the first electrically conductive layer, the second electrically conductive layer including silicon, carbon and nitride.

A system comprising:

• a plurality of memory partitions, individual ones of the memory partitions including:
• a substrate including control circuitry therein;
• and
• a semiconductor stack including:
• a first electrically conductive layer electrically coupled to the control circuitry of the substrate and including a metal;
• a second electrically conductive layer between the substrate and the first electrically conductive layer, the second electrically conductive layer including one of a refractory metal, or a combination including silicon, carbon and nitride;
• a memory element layer disposed on the first electrically conductive layer, the memory element layer including a phase change material;
• a third electrically conductive layer disposed on the memory element layer, wherein the first electrically conductive layer defines a plurality of first address lines, the third electrically conductive layer defines a plurality of second address lines, individual ones of the memory element layer between respective pairs of the first address lines and the second address lines, the memory element layer and first and second address lines together defining an array of pillars corresponding to an array of memory cells of said individual ones of the memory partitions;
• and
• a storage device controller coupled to the memory partitions to receive memory requests from a processor, and to access the memory cells based on the memory requests.