Semiconductor device and electronic system including the same

A semiconductor device comprising:

• a substrate including a memory cell region and a connection region;
• a plurality of gate electrodes in the memory cell region of the substrate and arranged apart from one another in a vertical direction perpendicular to a top surface of the substrate, the plurality of gate electrodes including at least one ground selection line and a plurality of word lines arranged at a vertical level which is higher than the at least one ground selection line, and the at least one ground selection line including a plurality of ground selection line cut regions;
• a pair of gate stack separation insulation layers passing through the plurality of gate electrodes and extending in a first horizontal direction in the memory cell region and the connection region of the substrate;
• a plurality of channel structures arranged in the memory cell region of the substrate to pass through the plurality of gate electrodes and extend in the vertical direction;
• a pad structure including a plurality of pad layers in the connection region of the substrate and connected to respective ones of the plurality of gate electrodes, the pad structure including a first pad group including a plurality of first pad layers arranged in a staircase shape in the first horizontal direction, a second pad group including a plurality of second pad layers arranged in a staircase shape in the first horizontal direction, and a third pad group including a plurality of third pad layers arranged in a staircase shape in the first horizontal direction;
• a plurality of ground selection line insulation layers respectively filling the plurality of ground selection line cut regions of the at least one ground selection line;
• and
• a plurality of dummy stack opening portions between the pair of gate stack separation insulation layers to pass through the plurality of gate electrodes and extend in the first horizontal direction, and
• each of the plurality of ground selection line insulation layers vertically overlap the second pad group without vertically overlapping the first pad group.

An electronic system comprising:

• a main substrate;
• a semiconductor device on the main substrate;
• and
• a controller electrically connected to the semiconductor device on the main substrate, the semiconductor device comprising
• a substrate including a memory cell region and a connection region;
• a plurality of gate electrodes in the memory cell region of the substrate and arranged apart from one another in a vertical direction perpendicular to a top surface of the substrate, the plurality of gate electrodes including at least one ground selection line and a plurality of word lines arranged at a vertical level which is higher than the at least one ground selection line;
• a pair of gate stack separation insulation layers passing through the plurality of gate electrodes and extending in a first horizontal direction in the memory cell region and the connection region of the substrate;
• and
• a pad structure including a plurality of pad layers in the connection region of the substrate, connected to respective ones of the plurality of gate electrodes, arranged in a staircase shape in the first horizontal direction, and arranged in a staircase shape in a second horizontal direction vertical to the first horizontal direction,
• the at least one ground selection line comprising a plurality of ground selection line cut regions, and each of the plurality of ground selection line cut regions being arranged apart from edges of the plurality of pad layers in the second horizontal direction.