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US 2023/0422506 A1Published application
Large grain and halogen-free silicon cell channel for 3d nand string
AssigneeIntel Corporation
InventorJessica S. Kachian
Life of this patent
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Abstract
An example of an apparatus may include an array of linear cell channels and a string of NAND memory cells arranged along a cell channel of the array of linear cell channels, where a polysilicon cell channel layer comprises material with less than E17 halogen atoms per cubic centimeter, where a thickness of the polysilicon cell channel layer is less than or equal to 25 nanometers, and where an area-weighted grain height mean of the polysilicon cell channel layer is greater than 30 nanometers. Other examples are disclosed and claimed.
Claims20
An apparatus, comprising:
- an array of linear cell channels;
- and
- a string of NAND memory cells arranged along a cell channel of the array of linear cell channels, wherein a polysilicon cell channel layer comprises material with less than E17 halogen atoms per cubic centimeter, wherein a thickness of the polysilicon cell channel layer is less than or equal to 25 nanometers, and wherein an area-weighted grain height mean (AWGHM) of the polysilicon cell channel layer is greater than 30 nanometers.
A memory device, comprising:
- a controller;
- and
- NAND memory coupled to the controller, the NAND memory comprising:
- an array of vertical NAND strings, wherein a polysilicon vertical cell channel of the array includes a plurality of NAND cells arranged along the polysilicon vertical cell channel with a tunnel oxide layer disposed between the plurality of NAND cells and the polysilicon vertical cell channel, and wherein the polysilicon vertical cell channel comprises less than E17 halogen atoms per cubic centimeter, wherein a thickness of the polysilicon vertical cell channel is less than or equal to 25 nanometers, and wherein an area-weighted grain height mean (AWGHM) of the polysilicon vertical cell channel is greater than 30 nanometers.
1 more element
A system, comprising:
- a processor;
- and
- a three-dimensional (3D) NAND memory device coupled to the processor, the 3D NAND memory device comprising:
- 3D NAND media comprising an array of vertical NAND strings, wherein a polysilicon vertical cell channel of the array includes a plurality of NAND cells arranged along the polysilicon vertical cell channel with a dielectric material disposed between the plurality of NAND cells and the polysilicon vertical cell channel, and wherein the polysilicon vertical cell channel comprises less than E17 halogen atoms per cubic centimeter, wherein a thickness of the polysilicon vertical cell channel is less than or equal to 25 nanometers, and wherein an area-weighted grain height mean (AWGHM) of the polysilicon vertical cell channel is greater than 30 nanometers.
1 more element
Dependencies are inferred from the claim text.