Semiconductor devices and data storage systems including the same

A semiconductor device, comprising:

• a peripheral circuit structure comprising a first substrate;
• and
• a memory cell structure on the peripheral circuit structure,
• wherein the memory cell structure comprises:
• a second substrate having a first region and a second region;
• a first horizontal conductive layer on the first region of the second substrate;
• a horizontal insulating layer on the second region of the second substrate and spaced apart from the first horizontal conductive layer;
• a second horizontal conductive layer covering the first horizontal conductive layer and the horizontal insulating layer;
• gate electrodes and first interlayer insulating layers that are alternately stacked so the gate electrodes are spaced apart from each other in a vertical direction perpendicular to an upper surface of the second substrate on the second horizontal conductive layer, the gate electrodes forming a step shape on the second region;
• a channel structure extending in the vertical direction on the first region, penetrating through the gate electrodes and the first interlayer insulating layers, and comprising a channel layer;
• isolation regions penetrating through the gate electrodes and the first interlayer insulating layers, extending in a first horizontal direction, and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction;
• and
• an upper support structure on the gate electrodes and having through-regions on the isolation regions, and
• wherein each of the first interlayer insulating layers comprises a first portion having a first thickness and a second portion having a thickness that decreases with increasing distance from the first portion toward the isolation regions, and
• wherein a boundary surface between the first portion and the second portion is vertically offset from side surfaces of the gate electrodes.

A data storage system, comprising:

• a semiconductor storage device comprising a peripheral circuit structure which comprises a first substrate and circuit devices on the first substrate, a through wiring region on the peripheral circuit structure, a barrier structure surrounding a side surface of the through wiring region, and an input/output pad electrically connected to the circuit devices;
• and
• a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device,
• wherein the semiconductor storage device comprises:
• a second substrate having a first region and a second region;
• gate electrodes and first interlayer insulating layers that are alternately stacked so the gate electrodes are spaced apart from each other in a vertical direction perpendicular to an upper surface of the second substrate on the first region of the second substrate, the gate electrodes extending from the first region to the second region, and forming a step shape on the second region;
• a channel structure penetrating through the gate electrodes on the first region and comprising a channel layer;
• and
• isolation regions penetrating through the gate electrodes,
• wherein the through wiring region comprises:
• second interlayer insulating layers and sacrificial insulating layers alternately stacked on the second region;
• and
• a through contact plug penetrating through the second interlayer insulating layers and the sacrificial insulating layers, and electrically connected to the circuit devices, and
• wherein the barrier structure comprises a plurality of protrusions extending into the sacrificial insulating layers.