Semiconductor memory device

A semiconductor memory device comprising:

• a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, and that includes a memory region and a staircase region arranged in a first direction that intersects a stacking direction of the plurality of conductive layers;
• a plate-like portion that extends in the stacked body in the stacking direction and in the first direction, and divides the stacked body in a second direction that intersects the stacking direction and the first direction;
• a first staircase portion that is arranged in the staircase region at a position that overlaps the plate-like portion in the stacking direction, in which the plurality of conductive layers is terraced in the first direction;
• a second staircase portion and a third staircase portion arranged in the staircase region on both sides in the second direction of the plate-like portion, and having structures in each of which the plurality of conductive layers is terraced, and that are mutually inverted in the second direction with respect to the plate-like portion;
• a plurality of first pillars arranged in the memory region on one side in the second direction of the plate-like portion and along the plate-like portion, and extending in the stacked body in the stacking direction;
• a plurality of second pillars arranged in the memory region on another side in the second direction of the plate-like portion and along the plate-like portion, and extending in the stacked body in the stacking direction;
• a plurality of first lower plugs arranged above the stacked body, and individually connected to the plurality of first pillars;
• a plurality of second lower plugs arranged above the stacked body, and individually connected to the plurality of second pillars;
• a plurality of first upper plugs arranged above the plurality of first lower plugs, and individually connected to the plurality of first lower plugs;
• and
• a plurality of second upper plugs arranged above the plurality of second lower plugs, and individually connected to the plurality of second lower plugs, wherein
• center positions in the second direction of the plurality of first lower plugs are individually arranged at different positions in the second direction relative to center positions in the second direction of the plurality of first upper plugs to be connected, and
• the plurality of second lower plugs is individually arranged at positions inverted in the second direction from respective positions of the plurality of first lower plugs, with respect to the plate-like portion.