Semiconductor memory device

A semiconductor memory device comprising:

• a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, the stacked body including a memory region and a staircase region arranged in a first direction that intersects a stacking direction of the plurality of conductive layers;
• a plate-like portion that extends in the stacked body in the stacking direction and in the first direction, and divides the stacked body in a second direction that intersects the stacking direction and the first direction;
• a plurality of first pillars dispersedly arranged in the memory region and extending in the stacked body in the stacking direction;
• a first staircase portion that is arranged in the staircase region at a position that overlaps the plate-like portion in the stacking direction, in which the plurality of conductive layers is terraced in the first direction;
• a second staircase portion and a third staircase portion arranged in the staircase region on both sides in the second direction of the plate-like portion, and having structures in each of which the plurality of conductive layers is terraced, and that are mutually inverted in the second direction with respect to the plate-like portion;
• and
• a plurality of first contacts arranged in the staircase region on one side in the second direction of the plate-like portion and along the plate-like portion, and individually connected to at least lower layers of conductive layers among the plurality of terraced conductive layers in the first staircase portion, wherein
• positions of placement of the plurality of first contacts in the second direction come closer to the plate-like portion as a first contact of the plurality of first contacts is connected to a conductive layer in one or more lower layers, among the conductive layers to which the plurality of first contacts is connected.

A semiconductor memory device comprising:

• a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, the stacked body including a memory region and a staircase region arranged in a first direction that intersects a stacking direction of the plurality of conductive layers;
• a plate-like portion that extends in the stacked body in the stacking direction and in the first direction, and divides the stacked body in a second direction that intersects the stacking direction and the first direction;
• a plurality of first pillars dispersedly arranged in the memory region and extending in the stacked body in the stacking direction;
• a first staircase portion that is arranged in the staircase region at a position that overlaps the plate-like portion in the stacking direction, in which the plurality of conductive layers is terraced in the first direction;
• a second staircase portion and a third staircase portion arranged in the staircase region on both sides in the second direction of the plate-like portion, and having structures in each of which the plurality of conductive layers is terraced, and that are mutually inverted in the second direction with respect to the plate-like portion;
• a first isolation layer that penetrates, among the plurality of conductive layers, a topmost conductive layer or penetrates the topmost conductive layer and at least one more conductive layer that is consecutive to the topmost conductive layer in the stacking direction, extends in the memory region on one side in the second direction of the plate-like portion and along the plate-like portion to selectively isolate in the second direction one or more conductive layers that include the topmost conductive layer;
• and
• a second isolation layer that penetrates the topmost conductive layer or penetrates the topmost conductive layer and the at least one more conductive layer, extends in the memory region on another side in the second direction of the plate-like portion and along the plate-like portion, to selectively isolate in the second direction the one or more conductive layers, wherein
• the first isolation layer includes a portion that extends along the plate-like portion at a first position with a distance in the second direction from the plate-like portion continuously varied depending on positions in the first direction, and
• the second isolation layer includes a portion that extends along the plate-like portion at a second position that is inverted in the second direction from the first position of the first isolation layer with respect to the plate-like portion.