Integrated circuit structures having memory with backside dram and power delivery

An integrated circuit structure, comprising:

• a front-side structure comprising:
• a device layer having a plurality of fin-based transistors;
• and
• a plurality of metallization layers above the fin-based transistors of the device layer;
• and
• a backside structure below the fin-based transistors of the device layer, the backside structure including a plurality of dynamic random access memory (DRAM) devices.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a front-side structure comprising:
• a device layer having a plurality of nanowire-based transistors;
• and
• a plurality of metallization layers above the nanowire-based transistors of the device layer;
• and
• a backside structure below the nanowire-based transistors of the device layer, the backside structure including a plurality of dynamic random access memory (DRAM) devices.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a front-side structure comprising:
• a device layer having a plurality of fin-based transistors;
• and
• a plurality of metallization layers above the fin-based transistors of the device layer;
• and
• a backside structure below the fin-based transistors of the device layer, the backside structure including a plurality of dynamic random access memory (DRAM) devices.