Integrated circuit semiconductor device

An integrated circuit semiconductor device comprising:

• a first active fin on a substrate;
• a first multi-bridge channel transistor on the first active fin, the first multi-bridge channel transistor includes a first gate electrode;
• a second active fin on the substrate and spaced apart from the first active fin;
• and
• a second multi-bridge channel transistor on the second active fin, the second multi-bridge channel transistor includes a second gate electrode that is directly connected to the first gate electrode, a recess region that is recessed in surfaces of the first gate electrode and the second gate electrode and is arranged between the first gate electrode and the second gate electrode,
• wherein a first height of a first sidewall of the first gate electrode is greater than a second height of a second sidewall of the first gate electrode adjacent to the recess region and opposite the first sidewall, and
• wherein a third height of a third sidewall of the second gate electrode is greater than a fourth height of a fourth sidewall of the second gate electrode adjacent to the recess region and opposite the third sidewall.

An integrated circuit semiconductor device comprising:

• a first active fin on a substrate;
• a first multi-bridge channel transistor on the first active fin, the first multi-bridge channel transistor includes a first gate electrode;
• a second active fin on the substrate and spaced apart from the first active fin;
• and
• a second multi-bridge channel transistor on the second active fin, the second multi-bridge channel transistor includes a second gate electrode that is directly connected to the first gate electrode, a recess region that is recessed in surfaces of the first gate electrode and the second gate electrode and is arranged between the first gate electrode and the second gate electrode,
• wherein a first width of a first sidewall of the first gate electrode is less than a second width of a second sidewall of the first gate electrode adjacent to the recess region and opposite the first sidewall, a third width of a third sidewall of the second gate electrode is less than a fourth width of a fourth sidewall of the second gate electrode adjacent to the recess region and opposite the third sidewall,
• wherein a first height of the first sidewall of the first gate electrode is greater than a second height of the second sidewall of the first gate electrode adjacent to the recess region and opposite the first sidewall, and a third height of the third sidewall of the second gate electrode is greater than a fourth height of the fourth sidewall of the second gate electrode adjacent to the recess region and opposite the third sidewall.