Memory device with unique read and/or programming parameters

A method of operating a memory device, comprising the steps of:

• preparing a memory block that includes a plurality of memory cells arranged in a plurality of word lines;
• determining if the memory block is in the multi-bit per memory cell mode or in the single-bit per memory cell mode;
• and
• during a programming operation on a selected word line of the plurality of word lines, at least one of;
• applying a first VSGD voltage to a source gate drain transistor in response to the memory block being in the multi-bit per memory cell mode, or applying a second VSGD voltage to the source gate drain transistor in response to the memory block being in the multi-bit per memory cell mode, the first VSGD voltage being different than the second VSGD voltage, and
• applying a first inhibit voltage to a plurality of bit lines coupled to memory cells to be inhibited from programming in response to the memory block being in the multi-bit per memory cell mode, or applying a second inhibit voltage to the plurality of bit lines coupled to memory cells to be inhibited from programming in response to the memory block being in the multi-bit per memory cell mode, the first inhibit voltage being different than the second inhibit voltage.

A memory device, comprising:

• a memory block comprising a plurality of memory cells arranged in a plurality of word lines, the memory block being configured to operate in a multi-bit per memory cell mode and to operate in a single-bit per memory cell mode;
• control circuitry configured to program data into the memory cells of the memory block and to read data from the memory cells of the memory block, the control circuitry being configured to:
• determine if the memory block is operating in the multi-bit per memory cell mode or in the single-bit per memory cell mode,
• in response to the memory block being in the multi-bit per memory cell mode applying at least one of a first VREADK voltage to at least one word line immediately adjacent a selected word line or a first VSGD voltage to a source gate drain transistor or a first inhibit voltage to at least one unselected bit line coupled to a memory cell being inhibited from programming, and
• in response to the memory block being in the single-bit per memory cell mode, applying at least one of a second VREADK voltage to the at least one word line immediately adjacent the selected word line or a second VSGD voltage to the source gate drain transistor or a second inhibit voltage to the at least one unselected bit line;
• and
• wherein the first VREADK voltage is different than the second VREADK voltage and the first VSGD voltage is different than the second VSGD voltage and the first inhibit voltage is different than the second inhibit voltage.