Memory chip and memory system including the same

A memory chip comprising:

• a plurality of storage blocks each including a plurality of memory cells;
• and
• a logic circuit configured to pair a pair of storage blocks among the plurality of storage blocks, the pair of storage blocks including a storage block having a kth highest operating current among the plurality of storage blocks and a storage block having a kth lowest operating current among the plurality of storage blocks, where k is a natural number, allocate respective block address codes having a bit inversion relationship with each other to the pair of storage blocks, and control the plurality of storage blocks using an external address code summary or using a first address code having the bit inversion relationship with regard to the external address code, according to an addressing mode.

A memory system comprising:

• a plurality of memory chips including a plurality of storage blocks, each of the plurality of memory chips configured to support a first addressing mode using a plurality of address codes allocated in order of operating current magnitudes of the plurality of storage blocks, and a second addressing mode in which the plurality of address codes are allocated in a reverse order of the operating current magnitudes of the plurality of storage blocks;
• and
• a processor configured to determine partial memory chips of the plurality of memory chips as first memory chips operating in the first addressing mode, and determine remaining memory chips of the plurality of memory chips as second memory chips operating in the second addressing mode, and provide an access command and a common address code to the first memory chips and the second memory chips.