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US 2023/0420014 A1Published application
Computing in memory electronic device capable of supporting current based analog multiply-accumulation operations and time based analog-to-digital conversion
AssigneeKorea University Research and Business Foundation
InventorsJongsun PARK, Hyunchul PARK, Kyeongho LEE
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Abstract
Embodiments of the present disclosure described herein relate to a computing in memory electronic device that supports current based analog operations and time based analog-to-digital conversion.
Claims10
An electronic device comprising:
- a memory cell array including a plurality of memory cells configured to perform a product operation of an input signal applied through a plurality of operation word lines and a pre-stored weight and to output a first output signal according to the product operation to a plurality of operation bit lines;
- a dummy cell array including a plurality of dummy cells configured to generate a reference signal and to output the reference signal to a plurality of dummy bit lines;
- a plurality of VTC circuits configured to receive a second output signal obtained by summing the first output signal through the plurality of operation bit lines and the reference signal and to convert the second output signal and the reference signal into a time domain;
- and
- a plurality of TDC circuits configured to compare the second output signal with the reference signal and to convert the second output signal into a digital domain based on a result of the comparison.
2 more elements
An electronic device comprising:
- a control circuit configured to generate a first enable signal, a second enable signal, and a dummy word line signal;
- a driver circuit configured to generate an input signal based on the first enable signal and to transfer the input signal to a plurality of operation word lines;
- a memory cell array configured to perform a product operation of the input signal and a pre-stored weight and to output a first output signal according to the product operation to a plurality of operation bit lines;
- a dummy cell array configured to generate a reference signal based on the dummy word line signal and to output the reference signal to a plurality of dummy bit lines;
- a VTC array configured to receive a second output signal obtained by summing the first output signal through the plurality of operation bit lines and the reference signal and to convert the second output signal and the reference signal into a time domain;
- and
- a TDC array configured to compare the second output signal with the reference signal and to convert the second output signal into a digital domain based on a result of the comparison.
4 more elements
Dependencies are inferred from the claim text.