US 2023/0420004 A1 · BRIDGE CHIP, SEMICONDUCTOR STORAGE DEVICE, AND MEMORY SYSTEM

Abstract

A bridge chip includes a first selection circuit, a second selection circuit, and a control circuit. The first selection circuit determines an output destination of input data and an input flag indicating whether the input data is valid or invalid based on a first selection signal. The second selection circuit determines an output destination of the input data and the input flag output from the first selection circuit based on a second selection signal. The control circuit generates the first selection signal and the second selection signal, and outputs the first selection signal and the second selection signal to the first selection circuit and the second selection circuit, respectively.

Claims20

Dependent claims

A bridge chip comprising:

a first selection circuit configured to determine a first output destination of input data and an input flag, the input flag indicating whether the input data is valid or invalid, based on a first selection signal;
a second selection circuit configured to determine a second output destination of the input data and the input flag output from the first selection circuit, based on a second selection signal;
and
a control circuit configured to:
generate the first selection signal and the second selection signal, and
output the first selection signal and the second selection signal to the first selection circuit and the second selection circuit, respectively.

3 more elements

A semiconductor storage device comprising :

a bridge chip including:
a first selection circuit configured to determine a first output destination of input data and an input flag, the input flag indicating whether the input data is valid or invalid, based on a first selection signal,
a second selection circuit configured to determine a second output destination of the input data and the input flag output from the first selection circuit, based on a second selection signal, and
a control circuit configured to:
generate the first selection signal and the second selection signal, and
output the first selection signal and the second selection signal to the first selection circuit and the second selection circuit, respectively;
and
a plurality of memory chips that are connected to the bridge chip.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/177,955Filed 3 Mar 2023

Priority

JP 2022-10052522 Jun 2022

Published

28 Dec 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 7/10
Arrangements for writing information into, or reading information out from, a digital store: input/output [I/O] data interface arrangements, e.g.…
G11C 7/1087
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input latches
G11C 7/1093
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: input synchronization
G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…

Bridge chip, semiconductor storage device, and memory system

Life of this patent

Bridge chip, semiconductor storage device, and memory system

Life of this patent

Abstract

Claims20