US 2023/0418781 A1 · MULTICORE SYNCHRONIZATION MECHANISM FOR TIME CRITICAL RADIO SYSTEMS

Abstract

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture implements a data driven synchronization process to maintain synchronization between the programmable elements (PEs) of the programmable processing array. The hybrid architecture implements a timer-based solution to ensure data-driven synchronization between the PEs of the programmable processing array meets the time-based synchronization requirements of the overall system. The timers function to introduce a delay or latency to the time required by each of the PEs of the programmable processing array to perform their respective tasks, thereby forcing the hardware blocks to wait to receive the processed data samples output via the PEs and perform their hardware-based computations.

Claims20

Dependent claims

A system on a chip (SoC), comprising:

an array of processing elements, each one of the array of processing elements being configured to execute processing operations on an array of input data samples in accordance with received instructions to generate an array of output data samples, and to delay transmission of the array of output data samples until expiration of a predetermined time period;
and
a hardware accelerator configured to execute a predetermined processing function on each one of an array of output data samples that is sequentially received from the array of processing elements in accordance with a predetermined timing synchronization schedule to sequentially generate respective sets of processed data samples,
wherein the sequentially-generated respective sets of processed data samples are used to perform wireless data communications.

1 more element

A system on a chip (SoC), comprising:

an array of processing elements, comprising:
a first subset of processing elements, each processing element from among the first subset of processing elements being configured to execute processing operations on an array of input data samples in accordance with received instructions and to generate and transmit an array of output data samples;
a second subset of processing elements, each processing element from among the second subset of processing elements being configured to execute processing operations an array of input data samples in accordance with received instructions to generate an array of output data samples, and to delay transmission of the array of output data samples until expiration of a predetermined time period;
and
a hardware accelerator configured to execute a predetermined processing function on each one of an array of output data samples, which are sequentially received from the second subset of processing elements in accordance with a predetermined timing synchronization schedule to sequentially generate respective sets of processed data samples,
wherein the sequentially-generated respective sets of processed data samples are used to perform wireless data communications.

3 more elements

Dependencies are inferred from the claim text.

Multicore synchronization mechanism for time critical radio systems

Life of this patent

Multicore synchronization mechanism for time critical radio systems

Life of this patent

Abstract

Claims20