Flash memory device having a calibration mode

A method of operation in a flash integrated circuit (IC) memory device having an array of memory cells, the method comprising:

• initializing an interface to receive control, address and data signals, wherein, at boot-up, the interface is operable to receive, using an internal reference voltage, signals having a first voltage swing at a first signaling frequency;
• receiving a clock signal;
• receiving a first command using the clock signal, wherein the first command specifies calibration of the interface during a calibration mode, wherein the calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing, wherein the second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency;
• and
• the interface, during the calibration mode, receiving a calibration pattern at the second signaling frequency.

A flash integrated circuit (IC) memory device comprising:

• an array of memory cells to store data;
• a circuit to generate an internal reference voltage;
• and
• a receiver circuit including a plurality of receivers to receive control, address and data signals, the receiver circuit to receive a first command using a clock signal, wherein the first command specifies calibration of the receiver circuit during a calibration mode, wherein:
• at boot up, the receiver circuit is operable to receive, using the internal reference voltage, signals having a first voltage swing at a first signaling frequency;
• the clock signal operates at the first signaling frequency during boot-up;
• the calibration mode is used to calibrate the receiver circuit to operate at a second signaling frequency and receive signals having a second voltage swing;
• the second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency;
• and
• the receiver circuit, during the calibration mode, is to receive a calibration pattern at the second signaling frequency.

A flash integrated circuit (IC) memory device comprising:

• an array of memory cells to store data;
• a circuit to generate an internal reference voltage;
• a clock receiver circuit to receive a clock signal, wherein the clock signal operates at a first signaling frequency during boot-up;
• and
• an interface having a plurality of receiver circuits coupled to a plurality of pins, each receiver circuit of the plurality of receiver circuits having a first input and a second input, the first input of each receiver circuit coupled to a respective pin of the plurality of pins, and the second input of each receiver circuit to receive the internal reference voltage,
• wherein, at boot up, the interface is operable to receive, using the internal reference voltage, signals having a first voltage swing at the first signaling frequency, the interface to receive a first command that specifies calibration of the interface during a calibration mode, wherein the calibration mode is used to calibrate the interface to operate at a second signaling frequency and receive signals having a second voltage swing, wherein the second voltage swing is smaller than the first voltage swing and the second signaling frequency is higher than the first signaling frequency, and wherein the interface, during the calibration mode, is to receive a calibration pattern at the second signaling frequency.