PC-Based Memory Permissions
AssigneeApple Inc.
InventorsJeffry E. Gonion, Bernard J. Semeria
Life of this patent
Estimating the term…
Abstract
A memory permissions model for a processor that is based on the memory address accessed by an instruction as well as the program counter of the instruction. These permissions may be stored in permissions tables and indexed using the memory addresses of the instruction and the address of the memory locations that it accesses. Those indexes may be obtained from a page table in some cases. These memory permissions may be used in conjunction with other permissions, such as execute permissions and secondary execution privileges that are based on whether the instruction belongs to a particular instruction group.
Claims20
An apparatus, comprising:
- a processor that includes:
- a permission table circuit configured to store a plurality of permissions for accesses to memory, wherein the permission table circuit is indexed by a particular permission table index corresponding to a particular instruction to provide a particular permission for a particular memory access by the particular instruction;
- and
- a control circuit coupled to the permission table circuit and configured to generate the particular permission table index based on:
- a first value corresponding to a first memory address indicated by the particular instruction;
- and
- a second value corresponding to a second memory address at which the particular instruction is stored.
A method, comprising:
- receiving, in a processor of a computer system, a particular instruction to be executed by an execution pipeline circuit of the processor, the particular instruction including a reference to a first memory address and being located at a second memory address;
- storing, by the processor in a permission table, a plurality of permissions for accesses to memory of the computer system, wherein the permission table is indexed by a permission table index;
- and
- generating, by the processor, a particular permission table index for the particular instruction based on:
- a first value corresponding to the first memory address;
- and
- a second value corresponding to the second memory address;
- retrieving, by the processor from the permission table using the particular permission table index, a particular permission of the plurality of permissions for the particular instruction;
- and
- enforcing, by the processor during execution of the particular instruction, a final memory permission that is based on the particular permission.
An apparatus, comprising:
- a processor configured to execute computer program instructions, the processor including:
- a permission table circuit configured to store, in a set of permission tables, a plurality of permissions for accesses to a memory, wherein the set of permission tables are indexed by a permission table index;
- an execution pipeline circuit configured to receive a particular instruction for execution, the particular instruction specifying a first memory address to be accessed by the particular instruction and the particular instruction being located at a second memory address, wherein a control circuit of the execution pipeline circuit is configured to:
- generate a particular permission table index for the particular instruction based on the first memory address and the second memory address;
- retrieve, from the permission table circuit using the particular permission table index, a particular permission of the plurality of permissions for the particular instruction, the particular permission being specific to code executing at the second memory address and accessing a memory location at the first memory address;
- and
- enforce, during execution of the particular instruction, a final memory permission that is based on the particular permission.
Dependencies are inferred from the claim text.