Processor and method for designating a demotion target to be demoted from an in-core cache structure to an out-of-core cache structure

A processor, designating a demotion target to demote the demotion target from an in-core cache structure to an out-of-core cache structure, comprising:

• a first core, including a decoder, a memory order buffer, and the in-core cache structure;
• a last-level cache coupled to the first core;
• and
• an out-of-core cache table;
• wherein:
• the last-level cache is shared by the first core and the other cores of the processor;
• for each of the different memory addresses, the out-of-core cache table shows its cache status in the last-level cache and its cache status in each of the different cores of the processor;
• in response to a cache data demotion instruction supported by an instruction set architecture, the decoder outputs microinstructions, wherein the cache data demotion instruction is executed to designate the demotion target and demote the demotion target from the in-core cache structure to the out-of-core cache structure;
• according to the microinstructions, a demotion target designation request is transferred to the last-level cache through the memory order buffer to drive the last-level cache to query the out-of-core cache table;
• according to the demotion target's cache status in the first core obtained from the out-of-core cache table, the last-level cache outputs a snoop request to the first core to snoop on the demotion target and demote the demotion target from the in-core cache structure of the first core to the last-level cache.