Debug Trace of Cache Memory Requests

An apparatus, comprising:

• a plurality of processor circuits;
• a cache memory circuit;
• and
• a trace control circuit configured to, in response to activation of a particular debug mode:
• monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit;
• store, in allocated space in a trace buffer, information associated with a particular one of the monitored memory requests;
• and
• in response to a determination that available capacity in the trace buffer fails to satisfy a threshold level, assert a respective stall request signal to one or more of the processor circuits.

A method, comprising:

• in response to an activation of a particular debug mode, monitoring, by a trace control circuit, memory requests issued from one or more processor circuits;
• allocating, by the trace control circuit, locations in a trace buffer for at least a portion of the monitored memory requests;
• storing, by the trace control circuit in the locations in the trace buffer, information associated with processing of the portion of the monitored memory requests;
• and
• in response to an indication that the trace buffer fails to satisfy a threshold capacity, stalling at least one of the one or more processor circuits.

A system, comprising:

• a memory circuit;
• a cache memory circuit configured to issue memory requests to the memory circuit in response to a cache miss;
• a trace control circuit configured to, in response to activation of a particular debug mode:
• monitor memory requests issued by the cache memory circuit to the memory circuit;
• allocate locations in a trace buffer for particular ones of the monitored memory requests;
• and
• in response to a determination that the trace buffer does not have sufficient space, store information associated with processing of the particular memory requests in a fill buffer.