Static cmos-based full adder circuits

An apparatus comprising:

• an integrated circuit including a static complementary metal-oxide-semiconductor (CMOS) based Full Adder (FA) circuit,
• wherein the static CMOS based FA circuit includes:
• a carry generation circuit that comprises a first NAND logic circuit configured to receive a first input and a second input and to generate a carry;
• a carry propagation circuit that comprises a first boolean logic circuit configured to receive the first input, the second input, and a third input and to generate a propagated output;
• and
• a carry output generation circuit that comprises a second NAND logic circuit configured to receive the generated carry of the first NAND logic circuit and the propagated output of the first boolean logic circuit and to generate a final carry as an output,
• wherein the carry generation circuit and the carry propagation circuit are configured to collectively form the carry output generation circuit,
• wherein the static CMOS based FA circuit further includes a sum generation circuit that comprises a second boolean logic circuit, a first inverter, a third boolean logic circuit, and a second inverter and that is configured to generate a sum output,
• wherein the second boolean logic circuit includes the carry generation circuit and is configured to receive the first input, the second input, and the generated carry and to generate an exclusive NOR output,
• wherein the first inverter is configured to invert the exclusive NOR output of the second boolean logic circuit and to generate an inverted exclusive NOR output,
• wherein the third boolean logic circuit is configured to receive the exclusive NOR output, the inverted exclusive NOR output, the propagated output, and the third input and to generate the sum output, and
• wherein the second inverter is configured to invert the generated sum output.

An apparatus comprising:

• an integrated circuit including a static complementary metal-oxide-semiconductor (CMOS) based Full Adder (FA) circuit,
• wherein the static CMOS based FA circuit includes:
• a carry generation circuit that comprises a first NAND logic circuit configured to receive a first input and a second input and to generate a carry;
• a carry propagation circuit that comprises a first boolean logic circuit configured to receive the first input, the second input, and a third input and to generate a propagated output;
• and
• a carry output generation circuit that comprises a second NAND logic circuit configured to receive the generated carry of the first NAND logic circuit and the propagated output of the first boolean logic circuit and to generate a final carry as an output,
• wherein the carry generation circuit and the carry propagation circuit are configured to collectively form the carry output generation circuit,
• wherein the static CMOS based FA circuit further includes a sum generation circuit that comprises a second boolean logic circuit, an exclusive NOR logic circuit, and an inverter and that is configured to generate a sum output,
• wherein the second boolean logic circuit includes the carry generation circuit and is configured to receive the first input, the second input, and the generated carry and to generate an exclusive NOR output,
• wherein the exclusive NOR logic circuit is configured to receive the exclusive NOR output and the third input and to generate the sum output, and
• wherein the inverter is configured to generate an inverted sum output by inverting the sum output generated by the exclusive NOR logic circuit.