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US 2023/0418321 A1Published application
Fast power-up scheme for current mirrors
AssigneeTexas Instruments Incorporated
InventorSaurabh Pandey
Life of this patent
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Abstract
An automatic charge/discharge circuit is presented that allows a current mirror circuit with a high capacitance to quickly and automatically charge or discharge the capacitance in order to allow for a fast start-up power supply. The charge/discharge circuit automatically stops charging or discharging as the voltage on the capacitance approached a desired steady state.
Claims20
A power circuit comprising:
- a sense transistor comprising a first source, a first gate and a first drain;
- a bias transistor comprising a second source, a second gate and a second drain;
- and
- a discharge transistor comprising a third source, a third gate and a third drain;
- wherein the first gate is coupled to the second gate, the second drain and the third source;
- the first drain is coupled to the third gate;
- the third drain is coupled to a ground node;
- and
- the first source and second source are coupled to a voltage supply node.
6 more elements
A power circuit comprising:
- a sense transistor comprising a first source, a first gate and a first drain;
- a bias transistor comprising a second source, a second gate and a second drain;
- and
- a charge transistor comprising a third source, a third gate and a third drain;
- wherein the first gate is coupled to the second gate, the second drain and the third source;
- the first drain is coupled to the third gate;
- the third drain is coupled to a voltage supply node;
- and
- the first source and second source are coupled to a ground node.
6 more elements
An integrated circuit, comprising:
- a sense transistor comprising a first source, a first gate and a first drain;
- a bias transistor comprising a second source, a second gate and a second drain;
- and
- a charge/discharge transistor comprising a third source, a third gate and a third drain;
- an enable transistor comprising a fourth source, a fourth gate and a fourth drain;
- an output transistor comprising a fifth source, a fifth gate and a fifth drain;
- wherein the first gate is coupled to the second gate, the second drain, the third source, the fourth drain and the fifth gate;
- the first drain is coupled to the third gate;
- the first source is coupled to the second source and the fourth source and fifth source;
- and the fourth gate is coupled to an enable node.
7 more elements
Dependencies are inferred from the claim text.