In-line electrical detection of defects at wafer level
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Hsuan Huang, Chien-Liang Chen, Pei-Hsuan Lee
Life of this patent
Estimating the term…
Abstract
In a semiconductor manufacturing method includes providing a plurality of patterns on a semiconductor substrate. The patterns include an NMOS structure arranged next to an N+/N well structure, and/or a PMOS structure arranged next to a P+/P well structure. The method further includes: receiving a plurality of images by applying an electron beam to the patterns; and transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns.
Claims20
A semiconductor manufacturing method, comprising:
- providing a plurality of patterns on a semiconductor substrate, wherein the patterns include an NMOS structure comprising at least one active structure formed with P-type doping in contact with at least one source/drain structure of N-type doping arranged next to an N+/N well structure comprising at least one active structure formed with N-type doping in contact at least one source/drain structure of N-type doping;
- receiving a plurality of images by applying an electron beam to the patterns;
- and
- transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns.
A device comprising:
- a wafer;
- and
- patterns disposed on a surface of the wafer, wherein the patterns include at least one of:
- an NMOS structure comprising at least one active structure formed with P-type doping in contact with at least one source/drain structure of N-type doping arranged next to an N*/N well structure comprising at least one active structure formed with N-type doping in contact at least one source/drain structure of N-type doping;
- and/or
- a PMOS structure comprising at least one active structure formed with N-type doping in contact with at least one source/drain structure of P-type doping arranged next to a P+/P well structure comprising at least one active structure formed with P-type doping in contact at least one source/drain structure of P-type doping.
A semiconductor manufacturing method, comprising:
- providing a plurality of patterns on a semiconductor substrate, wherein the patterns include a PMOS structure comprising at least one active structure formed with N-type doping in contact with at least one source/drain structure of P-type doping arranged next to a P+/P well structure comprising at least one active structure formed with P-type doping in contact at least one source/drain structure of N-type doping;
- receiving a plurality of images by applying an electron beam to the patterns;
- and
- transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns.
Dependencies are inferred from the claim text.