3d semiconductor devices and structures with electronic circuit units

A 3D device, said device comprising:

• a first level comprising first transistors, said first level comprising a first interconnect;
• a second level comprising second transistors, said second level overlaying said first level;
• and
• at least four electronic circuit units (ECUs),
• wherein each of said at least four ECUs comprises a first circuit, said first circuit comprising a portion of said first transistors,
• wherein each of said at least four ECUs comprises a second circuit, said second circuit comprising a portion of said second transistors,
• wherein each of said at least four ECUs comprises a first vertical bus,
• wherein said first vertical bus provides electrical connections between said first circuit and said second circuit,
• wherein said second level is bonded to said first level,
• wherein said bonded comprises oxide to oxide bonding regions and metal to metal bonding regions, and
• wherein at least one of said metal to metal bonding regions overlays at least a portion of at least one of said ECUs.

A 3D device, said device comprising:

• a first level comprising first transistors, said first level comprising a first interconnect;
• a second level comprising second transistors, said second level overlaying said first level;
• and
• at least four electronic circuit units (ECUs),
• wherein each of said at least four ECUs comprises at least one processor and at least one memory array,
• wherein each of said at least four ECUs comprises a first circuit, said first circuit comprising a portion of said first transistors,
• wherein each of said at least four ECUs comprises a second circuit, said second circuit comprising a portion of said second transistors,
• wherein each of said at least four ECUs comprises a first vertical bus,
• wherein each of said at least four ECUs comprises at least one memory array,
• wherein said first vertical bus provides electrical connections between said first circuit and said second circuit,
• wherein said device comprises a plurality of capacitors,
• wherein said second level is bonded to said first level, and
• wherein said bonded comprises oxide to oxide bonding regions and metal to metal bonding regions.