Non-volatile memory including negative capacitance blocking oxide layer, operating method of the same and manufacturing method of the same

An operating method of a non-volatile memory comprising a tunneling oxide layer formed on a channel;

• a charge storage layer formed on one surface of the tunneling oxide layer;
• a negative capacitance blocking oxide layer in which a dielectric layer and an imprinted polarization layer are sequentially configured on one surface of the charge storage layer;
• and a gate formed on one surface of the negative capacitance blocking oxide layer, the operating method comprising:
• applying a positive voltage to the gate;
• switching an initially aligned polarization of the imprinted polarization layer in response to the positive voltage being applied to the gate;
• inducing a depolarization field that is in a direction opposite to that of an electric field of the switched polarization in the imprinted polarization layer as the initially aligned polarization of the imprinted polarization layer is switched;
• additionally inducing an internal field that is in a direction opposite to that of the depolarization field in the dielectric layer by the depolarization field of the imprinted polarization layer;
• and
• charging and boosting the negative capacitance blocking oxide layer based on the depolarization field of the imprinted polarization layer and the internal field of the dielectric layer.

A manufacturing method of a non-volatile memory, the manufacturing method comprising:

• forming a tunneling oxide layer on a channel;
• forming a charge storage layer on one surface of the tunneling oxide layer;
• forming a negative capacitance blocking oxide layer by sequentially configuring a dielectric layer and an imprinted polarization layer on one surface of the charge storage layer;
• and
• forming a gate on one surface of the negative capacitance blocking oxide layer.

A non-volatile memory in a three-dimensional (3D) structure, the non-volatile memory comprising:

• a channel formed to extend in a vertical direction;
• at least one tunneling oxide layer formed to contact the channel;
• at least one charge storage layer formed to contact the at least one tunneling oxide layer;
• at least one negative capacitance blocking oxide layer in which a dielectric layer and an imprinted polarization layer are sequentially configured to contact the at least one charge storage layer;
• and
• a plurality of gates formed to contact the at least one negative capacitance blocking oxide layer.

An operating method of a non-volatile memory in a three-dimensional (3D) structure comprising a channel formed to extend in a vertical direction;

• at least one tunneling oxide layer formed to contact the channel;
• at least one charge storage layer formed to contact the at least one tunneling oxide layer;
• at least one negative capacitance blocking oxide layer in which a dielectric layer and an imprinted polarization layer are sequentially configured to contact the at least one charge storage layer;
• and a plurality of gates formed to contact the at least one negative capacitance blocking oxide layer, the operating method comprising:
• applying a positive voltage to one gate among the plurality of gates;
• switching an initially aligned polarization of the imprinted polarization layer corresponding to the one gate in response to the positive voltage being applied to the one gate;
• inducing a depolarization field that is in a direction opposite to that of an electric field of the switched polarization in the imprinted polarization layer as the initially aligned polarization of the imprinted polarization layer is switched;
• additionally inducing an internal field that is in a direction opposite to that of the depolarization field in the dielectric layer by the depolarization field of the imprinted polarization layer;
• and
• charging and boosting the at least one negative capacitance blocking oxide layer based on the depolarization field of the imprinted polarization layer and the internal field of the dielectric layer.

A manufacturing method of a non-volatile memory in a three-dimensional (3D) structure, the manufacturing method comprising:

• forming a channel to extend in a vertical direction;
• forming at least one tunneling oxide layer to contact the channel;
• forming at least one charge storage layer to contact the at least one tunneling oxide layer;
• forming at least one negative capacitance blocking oxide layer by sequentially configuring a dielectric layer and an imprinted polarization layer to contact the at least one charge storage layer;
• and
• forming a plurality of gates to contact the at least one negative capacitance blocking oxide layer.