US 2023/0413556 A1Published application

Semiconductor memory device

AssigneeKioxia Corporation

InventorYasushi MURAKAMI

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Abstract

A semiconductor memory device includes: conductive layers stacked in a stacking direction; a semiconductor layer opposed to the conductive layers; contact electrodes connected to the conductive layers; and insulating members including outer peripheral surfaces surrounded by at least a part of the conductive layers. A first insulating member overlaps with a first contact electrode when viewed from the stacking direction. A second insulating member does not overlap with the contact electrodes when viewed from the stacking direction. A surface on one side in the stacking direction of the first contact electrode is in contact with a first conductive layer and the first insulating member. Insides of surfaces surrounding the second insulating member of at least a part of the conductive layers when viewed from the stacking direction are not provided with a conductive member or a semiconductor member.

Claims20

Dependent claims

A semiconductor memory device comprising:

a substrate including a first region and a second region arranged in a first direction;
a plurality of conductive layers stacked in a stacking direction intersecting with a surface of the substrate, and extending in the first direction across the first region and the second region;
a semiconductor layer disposed in the first region, extending in the stacking direction, and opposed to the plurality of conductive layers;
an electric charge accumulating film disposed between the plurality of conductive layers and the semiconductor layer;
a plurality of contact electrodes disposed in the second region, and connected to a plurality of terrace portions of the plurality of conductive layers arranged in the first direction via parts of outer edges of the plurality of conductive layers when viewed from the stacking direction;
and
a plurality of insulating members disposed in the second region, and including outer peripheral surfaces surrounded by at least a part of the plurality of conductive layers when viewed from the stacking direction, wherein
the plurality of insulating members include:
a first insulating member that overlaps with a first contact electrode of the plurality of contact electrodes when viewed from the stacking direction;
and
a second insulating member that does not overlap with any of the plurality of contact electrodes when viewed from the stacking direction,
a surface on one side in the stacking direction of the first contact electrode includes a contact surface in contact with a first conductive layer of the plurality of conductive layers, and a contact surface in contact with the first insulating member, and
insides of surfaces surrounding the second insulating member of at least a part of the plurality of conductive layers when viewed from the stacking direction are not provided with a conductive member or a semiconductor member.

10 more elements

A semiconductor memory device comprising:

a substrate including a first region and a second region arranged in a first direction;
a plurality of conductive layers stacked in a stacking direction intersecting with a surface of the substrate, and extending in the first direction across the first region and the second region;
a semiconductor layer disposed in the first region, extending in the stacking direction, and opposed to the plurality of conductive layers;
an electric charge accumulating film disposed between the plurality of conductive layers and the semiconductor layer;
a plurality of contact electrodes disposed in the second region, and connected to a plurality of terrace portions of the plurality of conductive layers arranged in the first direction via parts of outer edges of the plurality of conductive layers when viewed from the stacking direction;
and
a plurality of insulating members disposed in the second region, and including outer peripheral surfaces surrounded by at least a part of the plurality of conductive layers when viewed from the stacking direction, wherein
at least two insulating members of the plurality of insulating members overlap with a first contact electrode of the plurality of contact electrodes when viewed from the stacking direction.

5 more elements

A semiconductor memory device comprising:

a substrate including a first region and a second region arranged in a first direction;
a plurality of conductive layers stacked in a stacking direction intersecting with a surface of the substrate, and extending in the first direction across the first region and the second region;
a semiconductor layer disposed in the first region, extending in the stacking direction, and opposed to the plurality of conductive layers;
an electric charge accumulating film disposed between the plurality of conductive layers and the semiconductor layer;
a plurality of contact electrodes disposed in the second region, and connected to a plurality of terrace portions of the plurality of conductive layers arranged in the first direction via parts of outer edges of the plurality of conductive layers when viewed from the stacking direction;
and
a plurality of insulating members disposed in the second region, and including outer peripheral surfaces surrounded by at least a part of the plurality of conductive layers when viewed from the stacking direction, wherein
the plurality of insulating members include a first insulating member that overlaps with a first contact electrode of the plurality of contact electrodes when viewed from the stacking direction,
a center position of the first contact electrode in a cross-sectional surface perpendicular to the stacking direction and including the first contact electrode is a first center position,
a center position of the first insulating member in a cross-sectional surface perpendicular to the stacking direction, and including the first insulating member and one of the plurality of conductive layers surrounding an outer peripheral surface of the first insulating member is a second center position, and
the first center position does not overlap with the second center position when viewed from the stacking direction.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/181,100Filed 9 Mar 2023
Priority: JP 2022-09964621 Jun 2022
Published: 21 Dec 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region
H10B 43/50
EEPROM devices comprising charge-trapping gate insulators: characterised by the boundary region between the core and peripheral circuit regions

Family

No related US applications are recorded in the indexed filing history.

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