Semiconductor memory device

A semiconductor memory device comprising:

• a substrate having a plurality of active regions;
• a plurality of word lines formed in the substrate and disposed in a plurality of word line trenches extending in a first direction and a plurality of buried insulating layers on the plurality of word lines;
• a plurality of cell pad patterns on the plurality of active regions;
• an insulating layer pattern on the plurality of buried insulating layers and the plurality of cell pad patterns;
• a plurality of isolation insulating patterns filling at least a portion of a plurality of isolation trenches extending in a second direction perpendicular to the first direction between the plurality of cell pad patterns and the insulating layer pattern;
• a plurality of bit line structures formed on the substrate and extending in the second direction;
• and
• a plurality of direct contact conductive patterns between the plurality of bit line structures and the plurality of active regions, wherein lower portions of the plurality of direct contact conductive patterns are located in the plurality of isolation trenches, respectively,
• wherein, each of the plurality of isolation insulating patterns comprises an isolation insulating line portion having a line shape and an isolation insulating spacer portion having a ring shape connected to each other and forming an integral body, the isolation insulating line portion and the isolation insulating spacer portion being disposed in alternating ones of the plurality of isolation trenches and extending in the second direction, and
• wherein the plurality of isolation insulating spacer portions at least partially surround the plurality of direct contact conductive patterns, respectively.

A semiconductor memory device comprising:

• a substrate having a plurality of active regions;
• a plurality of word lines formed in the substrate and disposed in a plurality of word line trenches extending in a first direction and a plurality of buried insulating layers on the plurality of word lines;
• a plurality of cell pad patterns on the plurality of active regions;
• an insulating layer pattern on the plurality of buried insulating layers and the plurality of cell pad patterns;
• a plurality of isolation insulating patterns filling at least a portion of a plurality of isolation trenches extending in a second direction perpendicular to the first direction between the plurality of cell pad patterns and the insulating layer pattern;
• a plurality of bit line structures formed on the substrate and extending in the second direction;
• a plurality of direct contact conductive patterns between the plurality of bit line structures and the plurality of active regions, wherein lower portions of the plurality of direct contact conductive patterns are located in the plurality of isolation trenches, respectively;
• a plurality of landing pads in contact with the plurality of cell pad patterns and extending to an upper portion of any one of two adjacent bit line structures among the plurality of bit line structures;
• and
• a plurality of capacitor structures including a plurality of lower electrodes in contact with the plurality of landing pads, an upper electrode, and a capacitor dielectric layer interposed between the plurality of lower electrodes and the upper electrode,
• wherein, each of the plurality of isolation insulating patterns comprises an isolation insulating line portion having a line shape and an isolation insulating spacer portion having a ring shape connected to each other and forming an integral body, the isolation insulating line portion and the isolation insulating spacer portion being disposed in alternating ones of the plurality of isolation trenches and extending in the second direction,
• wherein the plurality of isolation insulating spacer portions at least partially surround the plurality of direct contact conductive patterns, respectively, and
• wherein the plurality of cell pad patterns are separated and insulated from each other by the plurality of buried insulating layers and the plurality of isolation insulating patterns.