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US 2023/0413524 A1Published application
Semiconductor device including a forroelectric transistor
AssigneeSamsung Electronics Co., Ltd.
InventorKIJOON KIM
Life of this patent
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Abstract
A semiconductor device includes bit lines arranged on a substrate and extending in a first horizontal direction; channel layers respectively arranged on the plurality of bit lines; word lines respectively arranged on the plurality of channel layers, and extending in a second horizontal direction; and ferroelectric layers arranged between the plurality of channel layers and the plurality of word lines, wherein the plurality of ferroelectric layers comprise a base dielectric layer and a nanoparticle, the nanoparticle dispersed and arranged in the base dielectric layer, respectively, the nanoparticle has a core-shell structure including a core and a shell.
Claims20
A semiconductor device comprising:
- a plurality of bit lines arranged on a substrate and extending in a first horizontal direction;
- a plurality of channel layers respectively arranged on the plurality of bit lines;
- a plurality of word lines respectively arranged on the plurality of channel layers, and extending in a second horizontal direction;
- and
- a plurality of ferroelectric layers arranged between the plurality of channel layers and the plurality of word lines,
- wherein the plurality of ferroelectric layers comprise a base dielectric layer and a nanoparticle, the nanoparticle dispersed and arranged in the base dielectric layer, respectively,
- wherein the nanoparticle has a core-shell structure including a core and a shell,
- wherein the core includes a portion formed inside the nanoparticle and having a particular volume, and
- wherein the shell includes a portion corresponding to the nanoparticle except for the core and at least partially surrounds the core.
6 more elements
A semiconductor device comprising:
- a plurality of bit lines arranged on a substrate and extending in a first horizontal direction;
- a plurality of mold insulating layers respectively arranged on the plurality of bit lines, one or more of the plurality of mold insulating layers including a plurality of openings extending in a second horizontal direction substantially vertical to the first horizontal direction;
- a first cell transistor arranged on a first sidewall of an opening of the plurality of openings;
- and
- a second cell transistor arranged on a second sidewall of the opening,
- wherein the first cell transistor comprises:
- a first channel layer arranged on the first sidewall of the opening;
- a first ferroelectric material arranged on the first channel layer;
- and
- a first word line arranged on the first ferroelectric material and extending in the second horizontal direction,
- wherein the second cell transistor comprises:
- a second channel layer arranged on the second sidewall of the opening;
- a second ferroelectric material arranged on the second channel layer;
- and
- a second word line arranged on the second ferroelectric material and extending in the second horizontal direction,
- wherein the first ferroelectric material and the second ferroelectric material each comprises a base dielectric layer and nanoparticles, the nanoparticles having a core-shell structure including a core and a shell and the nanoparticles distributed and arranged in the base dielectric layer,
- wherein the core comprises a center of the nano particle, and
- wherein the shell comprises a portion except for the core in the nano particle and at least partially surrounds the core.
15 more elements
A semiconductor device comprising:
- a bit line arranged on a substrate and extending in a first horizontal direction;
- a channel layer including a first vertical extension portion arranged on the bit line and extending in a vertical direction substantially vertical to an upper surface of the substrate, a second vertical extension portion spaced apart from the first vertical extension portion and extending in the vertical direction, and a horizontal extension portion connected to bottom portions of the first vertical extension portion and the second vertical extension portion and extending in the first horizontal direction;
- a gate insulating layer arranged on the first vertical extension portion and the second vertical extension portion;
- a ferroelectric layer arranged on the gate insulating layer;
- and
- a plurality of word lines arranged on the ferroelectric layer and extending in a second horizontal direction substantially vertical to the first horizontal direction, the plurality of word lines including first word lines arranged on the first vertical extension portion with the gate insulating layer and the ferroelectric layer arranged therebetween and second word lines arranged on the second vertical extension portion with the gate insulating layer and the ferroelectric layer arranged therebetween,
- wherein the ferroelectric layer comprises a base dielectric layer and a nanoparticle, the nanoparticle dispersed and arranged in the base dielectric layer,
- the nanoparticle has a core-shell structure,
- the nanoparticle and the core have a spherical shape having a substantially concentric cross-section, and
- the shell includes a portion corresponding to the nanoparticle except for the core and at least partially surrounds the core.
7 more elements
Dependencies are inferred from the claim text.