US 2023/0413523 A1 · SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SEMICONDUCTOR STRUCTURE

Abstract

A semiconductor structure is provided. The semiconductor structure includes a plurality of memory cells located on a substrate. Each of the plurality of memory cells includes a transistor and a capacitor. The capacitor is electrically connected to the transistor. The capacitor includes a body portion, and at least one extension portion located on a side surface of the body portion, and the at least one extension portion is electrically connected to the body portion.

Claims17

Dependent claims

A semiconductor structure, comprising a plurality of memory cells located on a substrate, each of the plurality of memory cells comprising:

a transistor;
and
a capacitor electrically connected to the transistor, wherein the capacitor comprises a body portion, and at least one extension portion located on a side surface of the body portion, and the at least one extension portion is electrically connected to the body portion.

A method for forming a semiconductor structure, comprising:

providing a substrate;
forming a plurality of memory cells on the substrate, wherein forming the plurality of memory cells comprising:
forming a plurality of transistors on the substrate;
and
forming a plurality of capacitors, wherein each of the plurality of capacitors is electrically connected to a respective one of the plurality of transistors, each of the plurality of capacitors comprises a body portion, and an extension portion located on a side surface of the body portion, and the extension portion is electrically connected to the body portion.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/170,631Filed 17 Feb 2023

Priority

CN 202210704100.721 Jun 2022

Published

21 Dec 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10B 12/315
Having a storage electrode stacked over the transistor: with the capacitor higher than a bit line
H10D 1/042
Of capacitors having no potential barriers: using deposition processes to form electrode extensions
H10B 12/033
Making the capacitor or connections thereto: the capacitor extending over the transistor
H10B 12/0335
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug

Semiconductor structure and method for forming semiconductor structure

Life of this patent

Semiconductor structure and method for forming semiconductor structure

Life of this patent

Abstract

Claims17