Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells, each of the memory cells including at least an oxide semiconductor transistor;
• a first insulating layer disposed above the memory cell array;
• a first wiring layer disposed between the memory cell array and the first insulating layer;
• a second insulating layer extending in a first direction from the memory cell array toward the first insulating layer, wherein
• a first distance in the first direction from a lower end of the second insulating layer to the memory cell array is less than a second distance in the first direction from the first wiring layer to the memory cell array,
• a third distance in the first direction from an upper end of the second insulating layer to the memory cell array is greater than a fourth distance in the first direction from the first insulating layer to the memory cell array, and
• the second insulating layer has an annular cross-section;
• and
• a third insulating layer further disposed over the first insulating layer, a portion of the third insulating layer being surrounded by the second insulating layer.