Bit Cell with Isolating Wall

A method for forming a bit cell for a Static Random-Access Memory (SRAM) comprising forming, on a semiconductor substrate:

• a first pair of complementary transistors including a first pull-up transistor and a first pull-down transistor;
• a second pair of complementary transistors including a second pull-up transistor and a second pull-down transistor;
• a first pass-gate transistor;
• and
• a second pass-gate transistor;
• wherein each transistor of the bit cell comprises a semiconductor channel extending between respective source and drain regions along a respective horizontal channel track;
• wherein forming the first pair of complementary transistors comprises forming a first inverter gate electrode at the semiconductor channel of the first pair of complementary transistors, thereby providing a common gate electrode for the first pair of complementary transistors;
• wherein forming the second pair of complementary transistors comprises forming a second inverter gate electrode at the semiconductor channel of the second pair of complementary transistors, thereby providing a common gate electrode for the second pair of complementary transistors;
• wherein forming the first and second pass-gate transistors comprises forming a first pass-gate electrode forming a gate of the first pass-gate transistor, aligned with the first inverter gate electrode, and forming a second pass-gate electrode forming a gate of the second pass-gate transistor, aligned with the second inverter gate electrode;
• and
• wherein the method further comprises:
• forming a trench separating the first pass gate electrode from the first inverter gate electrode and filling the trench with a dielectric material, thereby forming a first dielectric wall separating the first pass gate and the first inverter gate electrode;
• and
• forming a trench separating the second pass gate electrode from the second inverter gate electrode and filling the trench with a dielectric material, thereby forming a second dielectric wall separating the second pass gate and the second inverter gate electrode.