Hardware Countermeasures Against DFA Attacks on AES Operations

An integrated circuit for performing an AES encryption algorithm having N rounds and for detecting a DFA attack, comprising:

• an integrated round circuit, wherein a round is defined as a time during which operations within the integrated round circuit are executed once, wherein the integrated round circuit comprises:
• a SubBytes circuit, a ShiftRows circuit, a MixColumns circuit, an adder, an input multiplexer and an adder multiplexer;
• wherein the SubBytes circuit and the ShiftRows circuit are performed sequentially before the MixColumns circuit;
• the adder is performed after the MixColumns circuit;
• the input multiplexer is used to select with an output of the adder or plaintext data;
• and the adder multiplexer is used to bypass the MixColumns circuit during a last round;
• at least one latch to hold interim data and results;
• a recheck multiplexer, having an output of one of the at least one latch as an input;
• a comparator to compare an output of one of the at least one latch to another value;
• and
• a controller, wherein the controller configures the integrated circuit to:
• perform a first (N-2) rounds;
• save the interim data after completion of the MixColumns circuit in the (N-2)nd round in one of the at least one latch;
• perform at least a portion of a (N-1)st round;
• save the results after completion of the MixColumns circuit in the (N-1)st round in one of the at least one latch;
• repeat a portion of the AES encryption algorithm using the interim data wherein the portion of the AES encryption algorithm that is repeated comprises all operations starting after the interim data was saved and ending with an operation after which the results were stored;
• compare an output of the repeated portion of the AES encryption algorithm with the saved results;
• and
• flag an error if the output of the repeated portion of the AES encryption algorithm (and the saved results do not match.