Delay locked loop circuitry and memory device

Abstract

Delay locked loop (DLL) circuitry system and a memory device are disclosed. The DLL circuitry system includes a timer unit and a DLL circuit coupled thereto. The timer unit is enabled to generate a DLL enable signal based on the signal instructing the entry into a low power consumption mode and a predefined timer condition. The DLL enable signal enables the DLL circuit to realign an internal clock signal with an external clock signal. In this way, the DLL circuit is avoided from being unable to align the internal clock signal with the external clock signal because the memory device enters the low power mode which causes the variation of the power supply voltage of the DLL circuit. Moreover, a read or write error that may occur when data is to be read or written immediately after exiting the low power consumption mode is also avoided.

Dependencies are inferred from the claim text.