Switching circuit, corresponding device and method

A device, comprising:

• a PWM modulator to receive an input signal and to produce therefrom a PWM-modulated drive signal;
• a circuit coupled with the PWM modulator, wherein said circuit comprises:
• a switching circuit stage comprising first and second half bridges, each half bridge comprising a high-side transistor and a low-side transistor with an output node between the high-side transistor and the low-side transistor, the output nodes of the first and second half bridges configured for supplying an electrical load;
• control circuitry configured, in response to the PWM-modulated drive signal, to control alternate switching sequences of the high-side and low-side transistors in the first and second half bridges wherein a first pair of transistors comprising the high-side transistor in one of the half bridges and the low-side transistor in the other of the half bridges is switched to a non-conductive state, and a second pair of transistors comprising the high-side transistor in the other of the half bridges and the low-side transistor in the one of the half bridges is switched to a conductive state;
• and
• a current flow line between the output nodes in the first half bridge and the second half bridge, the current flow line comprising an inductance having opposed terminals coupled to a first switch and a second switch, wherein the first switch and the second switch are selectively switchable between a non-conductive state and at least one conductive state;
• and
• wherein the control circuitry is configured:
• in a first operation mode where the switching circuit stage is operating at a first power level, to switch the first switch and the second switch to the at least one conductive state at intervals in said alternate switching sequences in response to switching the first pair of transistors to the non-conductive state and to switching the second pair of transistors to the conductive state;
• and
• in a second operation mode where the switching circuit stage is operating at a second power level lower than the first power level, to refrain from switching the first switch and the second switch to the at least one conductive state at intervals in said alternate switching sequences in response to switching the first pair of transistors to the non-conductive state and to switching the second pair of transistors to the conductive state;
• and
• respective low pass filter networks coupled to the output nodes of the first and second half bridges.

A method of operating a class-D amplifier, the method comprising:

• receiving an input signal;
• generating a PWM signal based on the input signal;
• alternatively switching first and second half-bridges of the class-D amplifier in an alternate switching sequence based on the PWM signal, the half-bridges having respective output nodes coupled to a load via respective filter networks, wherein alternatively switching the first and second half-bridges in the alternate switching sequence comprises:
• turning on a first pair of transistors of the half-bridges when a second pair of transistors of the half-bridges is off, and
• turning on the second pair of transistors when the first pair of transistors is off, wherein the first pair of transistors comprises a high-side transistor in one of the half-bridges and a low-side transistor in the other of the half-bridges, and the second pair of transistors comprises a high-side transistor in the other of the half-bridges and a low-side transistor in the one of the half-bridges;
• in a first operation mode when operating at a first power level, turning on a first switch coupled to the output node of the first half-bridge and a second switch coupled to the output node of the second half-bridge at intervals in the alternate switching sequence between turning off the first pair of transistors and turning non the second pair of transistors;
• and
• in a second operation mode when operating at a second power level lower than the first power level, refraining from turning on the first switch and the second switch at intervals in the alternate switching sequence between turning off the first pair of transistors and turning non the second pair of transistors;
• wherein an auxiliary inductance is coupled between the first switch and the second switch.