Quasi-resonant isolated voltage converter

A circuit comprising:

• a first transistor having a first control input and first and second current terminals;
• a second transistor having a second control input and third and fourth current terminals;
• a third transistor having a third control input and fifth and sixth current terminals;
• a fourth transistor having a fourth control input and seventh and eighth current terminals;
• a fifth transistor having a fifth control input and ninth and tenth current terminals, the ninth current terminal coupled to the second current terminal;
• a sixth transistor having a sixth control input and eleventh and twelfth current terminals, the fifth and sixth transistors are cross-coupled, the eleventh current terminal coupled to the fourth current terminal;
• a seventh transistor having a seventh control input and thirteenth and fourteenth current terminals, the thirteenth current terminal coupled to the tenth current terminal, and the fourteenth current terminal coupled to the fifth current terminal;
• an eighth transistor having an eighth control input and fifteenth and sixteenth current terminals, the seventh and eighth transistors are cross-coupled, the fifteenth current terminal coupled to the twelfth current terminal, and the sixteenth current terminal coupled to the seventh current terminals
• a first capacitive device coupled between the fifth current terminal and the sixth current terminal;
• and
• a second capacitive device coupled between the seventh current terminal and the eighth current terminal.

A voltage converter, comprising:

• a transformer having a primary winding and a secondary winding, the primary winding having first and second winding terminals;
• a switch network having a first, second, third, fourth, fifth, and sixth switch network terminals, the first switch network terminal coupled to the first winding terminal, and the second switch network terminal coupled to the second winding terminal;
• a first field-effect transistor (FET) having a first gate, first drain, and a first source, the first drain coupled to the third switch network terminal;
• a second FET having a second gate, a second drain, and a second source, the second drain coupled to the fourth switch network terminal;
• a third FET having a third gate, a third drain, a third source, the third drain coupled to the fifth switch network terminal;
• and
• a fourth FET having a fourth gate, a fourth drain, and a fourth source, the fourth drain coupled to the sixth switch network terminal, and wherein the switch network comprises:
• a fifth FET having a fifth gate, a fifth source, and a fifth drain, the fifth source coupled to the first drain;
• a sixth FET having a sixth gate, a sixth source, and a sixth drain, the sixth source coupled to the second drain, the sixth gate coupled to the fifth drain, and the sixth drain coupled to the fifth gate;
• a seventh FET having a seventh gate, a seventh source, and a seventh drain, the seventh drain coupled to the fifth drain and the seventh source coupled to the third drain;
• and
• an eighth FET having an eighth gate, an eighth source, and an eighth drain, the eighth drain coupled to the sixth source and to the seventh gate, the eighth gate coupled to the seventh drain, and the eighth source coupled to the fourth drain;
• wherein during a first time period the second FET, the third FET, the sixth FET, and the seventh FET are configured to be on and the first FET, the fourth FET, the fifth FET, and the sixth FET are configured to be off;
• and
• wherein during a second time period, the second FET, the third FET, the sixth FET, and the seventh FET are configured to be off and the first FET, the fourth FET, the fifth FET, and the sixth FET are configured to be on.