Vertical field effect transistor with strained channel

Abstract

A vertical field effect transistor with a strained channel includes a channel fin structure extending vertically from a substrate. The channel fin structure being composed of a stress liner embedded within a semiconductor channel layer. The stress liner induces an uniaxial strain along a vertical direction of the channel fin structure. A high-k material is disposed along sidewalls of the semiconductor channel layer followed by a workfunction metal and a gate material. A top source/drain region is located above a top portion of the channel fin structure, and a bottom source/drain region, formed within the substrate, is located adjacent to a bottom portion of the channel fin structure.

Dependencies are inferred from the claim text.