US 2023/0411513 A1Published application

Semiconductor device and semiconductor device manufacturing method

AssigneeLapis Semiconductor Co., Ltd.

InventorsTOMOMI YAMANOBE, YOSHINOBU TAKESHITA, KAZUTAKA KODAMA, MINAKO ORITU

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Abstract

A semiconductor device including: a first semiconductor layer having a first conductive type; a second semiconductor layer provided on the first semiconductor layer, the second semiconductor layer having a second conductive type that is a conductive type different from the first conductive type; an impurity region of the first conductive type formed at a surface of the second semiconductor layer; first electrodes contacting the impurity region, the second semiconductor layer, and the first semiconductor layer via a first insulating film; and second electrodes contacting the first electrodes via a second insulating film, and contacting the first semiconductor layer via a third insulating film, the second electrodes including PN junctions at borders between upper portions that contact the first semiconductor layer via the third insulating film and lower portions that contact the first semiconductor layer via the third insulating film.

Claims4

Dependent claims

A semiconductor device manufacturing method, comprising:

forming a first semiconductor layer having a first conductive type at a main surface of a semiconductor substrate;
forming first opening portions at an interior of the first semiconductor layer;
forming an insulating film at bottom surface portions and side wall portions of the first opening portions, and forming concave portions;
forming first electrodes having the first conductive type at bottom surface portions of the concave portions;
forming second electrodes having a second conductive type at upper portions of the first electrodes, the second conductive type is a conductive type different from the first conductive type;
forming third electrodes at an interior of the insulating film;
forming a second semiconductor layer having the second conductive type at the first semiconductor layer at peripheries of the first opening portions;
and
forming an impurity region having the first conductive type at an upper portion of the second semiconductor layer.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/231,377Filed 8 Aug 2023
Priority: JP 2018-02952822 Feb 2018
Published: 21 Dec 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 30/0291
Of double-diffused metal oxide semiconductor [DMOS] FETs: of vertical dmos [vdmos] fets
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 64/117
Field plates: recessed field plates, e.g. trench field plates or buried field plates

Family

Application16/280,250Division · filed 20 Feb 2019
Application18/231,377Division
US 11,764,294 B2Related patent
US 12,074,215 B2Related patent
US 2019/0259873 A1Published application
US 2023/0411513 A1This patent

From the US filing history. Foreign family members aren’t listed.

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