Gate Isolation Feature and Manufacturing Method Thereof

A method comprising:

• forming a first stack of semiconductor layers, a second stack of semiconductor layers and a third stack of semiconductor layers on a substrate, wherein the first, second and third stack of semiconductor layers each include a stack of alternating first and second semiconductor layers;
• forming a first dielectric fin structure on the substrate between the first and second stack of semiconductor layers and a second dielectric fin structure on the substrate between the second and third stack of semiconductor layers, the first dielectric fin structure having a different width than the second dielectric fin structure, wherein the first and second dielectric fin structures include respective top surfaces facing away from the substrate;
• removing the first semiconductor layers from the first, second and third stack of semiconductor layers;
• forming a first gate structure wrapping around the second semiconductor layers in the first stack of semiconductor layers, a second gate structure wrapping around the second semiconductor layers in the second stack of semiconductor layers and a third gate structure wrapping around the second semiconductor layers in the third stack of semiconductor layers;
• forming a conductive layer directly on the first gate structure, the first dielectric fin structure, the second gate structure, the second dielectric fin structure and the third gate structure such that the conductive layer extends continuously over the first gate structure, the first dielectric fin structure, the second gate structure, the second dielectric fin structure and the third gate structure;
• and
• forming a first dielectric cut feature through the conductive layer to the top surface of the first dielectric fin structure and a second dielectric cut feature through the conductive layer to the top surface of the second dielectric fin structure, wherein a portion of the top surface of the first dielectric fin structure is covered by the conductive layer after the forming of the first dielectric cut feature through the conductive layer to the top surface of the first dielectric fin structure.

A method comprising:

• forming a plurality of fin structures extending in a first direction;
• forming a plurality of dummy fin structures between the plurality of fin structures;
• forming a gate structure over the fin structures;
• recessing the gate structure to expose top surfaces of the dummy fin structures and to separate the gate structure into a plurality of gate structure segments positioned along a line extending in a second direction orthogonal to the first direction;
• depositing a conductive layer over the gate structure segments and the dummy fin structures, the conductive layer electrically connecting the gate structure segments;
• and
• forming a cut feature above at least one of the dummy fin structures to electrically isolate gate structure segments on both sides of the at least one of the dummy fin structures.