Semiconductor device

A semiconductor device, comprising:

• a substrate including an active pattern;
• a channel pattern on the active pattern, the channel pattern comprising a plurality of semiconductor patterns, which are vertically stacked to be spaced apart from each other;
• a source/drain pattern connected to the plurality of semiconductor patterns;
• a gate electrode including a plurality of gate electrode portions, a gate electrode portion interposed between adjacent ones of the semiconductor patterns;
• and
• a plurality of barrier patterns each comprising an epitaxial layer including single-crystalline silicon oxide,
• wherein a barrier pattern is interposed between each of the adjacent ones of the semiconductor patterns and a respective gate electrode portion,
• wherein each of the plurality of barrier patterns comprise silicon oxide,
• wherein an oxygen concentration of the silicon oxide has a value selected from a range between 7.0E18 atoms/cm3 and 1.3E19 atoms/cm3, and
• wherein a thickness of each of the plurality of barrier patterns has a value selected from a range between 30 Å and 40 Å.

A semiconductor device, comprising:

• a substrate including an active region;
• a device isolation layer defining an active pattern on the active region;
• a channel pattern and a source/drain pattern on the active pattern, the channel pattern comprising a plurality of semiconductor patterns, which are vertically stacked to be spaced apart from each other;
• a gate electrode on the semiconductor patterns, the gate electrode comprising a first portion, which is provided below the uppermost one of the semiconductor patterns, and a second portion, which is provided on the uppermost one of the semiconductor patterns;
• a first barrier pattern between the uppermost one of the semiconductor patterns and the first portion;
• a gate insulating layer between the uppermost one of the semiconductor patterns and the second portion;
• an inner spacer between the first portion and the source/drain pattern;
• a gate spacer on a side surface of the second portion;
• a gate capping pattern on a top surface of the gate electrode;
• an interlayer insulating layer on the gate capping pattern;
• an active contact provided to penetrate the interlayer insulating layer and electrically connected to the source/drain pattern;
• a metal-semiconductor compound layer interposed between the active contact and the source/drain pattern;
• a gate contact provided to penetrate the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode;
• a first metal layer on the interlayer insulating layer, the first metal layer comprising first interconnection lines, which are electrically and respectively connected to the active and gate contacts, and a power line;
• and
• a second metal layer on the first metal layer,
• wherein the second metal layer comprises second interconnection lines electrically connected to the first metal layer,
• the first barrier pattern comprises single-crystalline silicon oxide, and
• the gate insulating layer comprises amorphous silicon oxide.