Semiconductor electronic devices including sidewall barrier layers and methods of fabricating the same

A method of fabricating a semiconductor electronic device, the method comprising:

• providing a substrate;
• forming a patterned electrode structure on the substrate, the patterned electrode structure comprising:
• a first barrier layer disposed on the substrate;
• a metallic electrode layer disposed on the first barrier layer, the metallic electrode layer being formed of one or more of copper, gold, and silver;
• and
• a second barrier layer disposed on the upper surface of the metallic electrode layer, wherein the first barrier layer, the metallic electrode layer, and the second barrier layer are patterned such that a sidewall of the metallic electrode layer is exposed between the first barrier layer and the second barrier layer;
• heating the substrate to a deposition temperature of at least 300° C.;
• exposing the patterned electrode structure to a manganese precursor at the deposition temperature within a deposition chamber for a deposition period, wherein a pressure in the deposition temperature is at least 0.1 Torr during the deposition period, wherein the deposition period is at least 1 second and the manganese precursor selectively migrates the sidewall;
• and
• after exposing the substrate to the manganese precursor, exposing the patterned electrode structure to an oxide that reacts with the manganese precursor to form an MnOx barrier layer disposed locally on the sidewall.

A method of fabricating a thin film transistor, the method comprising:

• providing a substrate;
• depositing a gate electrode layer on a device surface of the substrate and patterning the gate electrode layer into a gate electrode;
• depositing a dielectric layer on the gate electrode layer;
• depositing a semiconductor on the dielectric layer;
• forming a patterned electrode structure on the channel, the patterned electrode structure comprising a first barrier layer disposed on the semiconductor layer, an electrode layer disposed on the first barrier layer, and a second barrier layer disposed on the electrode layer, wherein the electrode layer comprises a drain portion comprising a drain sidewall and a source portion comprising a source sidewall, the drain sidewall and the source sidewall being disposed over the gate electrode;
• simultaneously forming sidewall barrier layers extending over the source and gate sidewalls and an oxide-containing passivation layer on the patterned electrode structure, wherein simultaneously forming the sidewall barrier layers and the oxide-containing passivation layer comprising:
• placing the substrate and patterned electrode structure into a plasma enhanced chemical vapor deposition chamber in fluid communication with a bubbler containing a manganese precursor;
• flowing the manganese precursor into the deposition chamber for a predetermined period while the substrate and patterned electrode are heated to a deposition temperature;
• and
• flowing chemical components of the oxide-containing passivation layer into the deposition chamber such that an oxide reacts with the manganese precursor to form magnesium oxide sidewalls barrier layers on the source and gate sidewalls.