Methods of manufacturing semiconductor devices and semiconductor devices

A method of manufacturing a semiconductor device, comprising:

• forming a first fin structure and a second fin structure, in each of which first semiconductor layers and second semiconductor layers are alternately stacked over a substrate;
• forming sacrificial gate structures over the first fin structure and the second fin structure;
• etching a first source/drain region of the first fin structure, which is not covered by the sacrificial gate structures, thereby forming a first source/drain space, and etching a second source/drain region of the second fin structure, which is not covered by the sacrificial gate structures, thereby forming a second source/drain space;
• laterally etching ends of the first semiconductor layers in the first source/drain space and in the second source/drain space, respectively;
• forming an insulating layer on a sidewall of the first source/drain space and on a sidewall of the second source/drain space, respectively;
• partially etching the insulating layer, thereby forming one or more inner spacers on an etched end face of each of one or more first semiconductor layers and leaving a part of the insulating layer as a remaining insulating layer in the first source/drain space and in the second source/drain space, respectively;
• and
• forming a first source/drain epitaxial layer in the first source/drain space and a second source/drain epitaxial layer in the second source/drain space,
• wherein after the first source/drain epitaxial layer is formed, an end face of at least one of the second semiconductor layers is covered by the remaining insulating layer in the first source/drain space.

A semiconductor device comprising a first gate-all-around field effect transistor (GAA FET) and a second GAA FET, wherein:

• each of the first GAA FET and the second GAA FET includes:
• semiconductor nano sheets or nano wires disposed over and vertically arranged over a substrate;
• a gate structure;
• and
• a source/drain epitaxial layer,
• wherein a number of the semiconductor nano sheets or nano wires in contact with the source/drain epitaxial layer in the first GAA FET is smaller than a number of the semiconductor nano sheets or nano wires in contact with the source/drain epitaxial layer in the second GAA FET, and
• an air gap is disposed below the source/drain epitaxial layer in the first and second GAA FETs.