Semiconductor device

A semiconductor device, comprising:

• a first active pattern and a second active pattern on a substrate;
• a device isolation layer in a trench between the first active pattern and the second active pattern;
• a first channel pattern and a second channel pattern provided on the first and second active patterns, respectively, each of the first channel pattern and the second channel pattern comprising a plurality of stacked semiconductor patterns;
• and
• a gate electrode on the first channel pattern and the second channel pattern,
• wherein the device isolation layer, which is vertically overlapped with the gate electrode, comprises a first portion having a silicon concentration in a range of about 41 at % to about 45 at %, and
• a level difference between a top surface of each of the first active pattern and the second active pattern and a top surface of the first portion is larger than 0 Å and is smaller than or equal to about 200 Å.

A semiconductor device, comprising:

• a substrate including an active region;
• a device isolation layer between an adjacent pair of the active patterns, wherein the device isolation layer comprises a first portion and a second portion, and the first portion is on the second portion, such that the first and second portions overlap each other;
• a channel pattern and a source/drain pattern on the active pattern, the channel pattern comprising a plurality of semiconductor patterns, which are vertically stacked and spaced apart from each other;
• a gate electrode on the semiconductor patterns, the gate electrode comprising a portion between each adjacent pair of the plurality of semiconductor patterns;
• a first gate insulating layer between each of the semiconductor patterns and the portion of the gate electrode;
• a second gate insulating layer covering the active pattern and a top surface of the device isolation layer;
• a gate capping pattern on a top surface of the gate electrode;
• an interlayer insulating layer on the gate capping pattern;
• a gate contact provided through the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode;
• a first metal layer on the interlayer insulating layer, the first metal layer comprising first interconnection lines, which are electrically connected to the gate contact, and a power line;
• and
• a second metal layer on the first metal layer,
• wherein the second metal layer comprises second interconnection lines electrically connected to the first metal layer, and
• a silicon concentration of the first portion of the device isolation layer is higher than a silicon concentration of the second portion.