Field-effect transistor and method for manufacturing same

Afield-effect transistor comprising:

• a semiconductor substrate having a plurality of trenches on an upper surface;
• a gate insulating film covering an inner surface of the trench;
• and
• a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film, wherein
• the semiconductor substrate includes:
• a plurality of source regions having an n-type;
• a p-type body region;
• an n-type drift region;
• and
• a plurality of breakdown voltage regions having a p-type,
• the semiconductor substrate has an inter-trench range located between the plurality of trenches,
• each of the plurality of source regions is provided in a corresponding inter-trench range and is in contact with a corresponding gate insulating film,
• the body region extends over the inter-trench range, and is in contact with the gate insulating films on a lower side of the source region within the inter-trench range,
• the drift region is distributed over a range from the inter-trench range to a lower side of each trench, and is in contact with the gate insulating film on a lower side of the body region,
• the plurality of breakdown voltage regions is provided within the inter-trench range,
• the plurality of breakdown voltage regions is provided within a range surrounded by the drift region,
• the plurality of breakdown voltage regions is separated from the body region by the drift region,
• the plurality of breakdown voltage regions is arranged to form a plurality of rows extending in a first direction intersecting the plurality of trenches,
• in each of the rows, the plurality of breakdown voltage regions is arranged at interval in the first direction,
• the plurality of rows is spaced from each other in a second direction parallel to the trench;
• each of the breakdown voltage regions has a p-type impurity concentration higher than that of the body region, extends from an upper side of a lower end of each of the trenches to a lower side of the lower end of each of the trenches, and is spaced from the gate insulating film, and
• the drift region is in contact with the gate insulating film at a position between the breakdown voltage region and the gate insulating film.