Semiconductor package and method of manufacturing the same

A semiconductor package comprising:

• a first semiconductor chip including a first substrate having a first surface and a second surface, located opposite to each other, and including a redistribution structure located on the first surface, a first interconnection structure disposed on the second surface, through-electrodes passing through the first substrate and connecting the redistribution structure to the first interconnection structure, and first contact pads disposed on the redistribution structure;
• first conductive posts disposed on the first interconnection structure and electrically connected to the first interconnection structure;
• a first mold layer disposed on the first interconnection structure and having an upper surface, coplanar with upper ends of the first conductive posts;
• a second semiconductor chip including a second interconnection structure having a first region on which the first semiconductor chip is disposed and a second region, different from the first region, and second contact pads disposed on the first region of the second interconnection structure and respectively connected to the first contact pads, wherein the first surface of the first semiconductor chip is disposed to face the second interconnection structure;
• second conductive posts disposed on the second region of the second interconnection structure and electrically connected to the second interconnection structure;
• a second mold layer disposed on the second region of the second interconnection structure, and having an upper surface, coplanar with upper ends of the second conductive posts and the upper surface of the first mold layer;
• a passivation layer disposed on the first mold layer and the second mold layer;
• and
• a plurality of conductive connection structures passing through the passivation layer and respectively connected to the first and second conductive posts.

A semiconductor package comprising:

• a first semiconductor chip including a first substrate having a first surface and a second surface, located opposite to each other, and including a redistribution structure located on the first surface, a first interconnection structure disposed on the second surface, through-electrodes passing through the first substrate and connecting the redistribution structure to the first interconnection structure, and first contact pads disposed on the first interconnection structure;
• first conductive posts disposed on the redistribution structure and electrically connected to the redistribution structure;
• a first mold layer disposed on the redistribution structure and having an upper surface, coplanar with upper ends of the first conductive posts;
• a second semiconductor chip including a second interconnection structure having a first region on which the first semiconductor chip is disposed and a second region, different from the first region, and second contact pads disposed on the first region of the second interconnection structure and respectively connected to the first contact pads, wherein the second surface of the first semiconductor chip is disposed to face the second interconnection structure;
• second conductive posts disposed on the second region of the second interconnection structure and electrically connected to the second interconnection structure;
• a second mold layer disposed on the second region of the second interconnection structure, and having an upper surface, coplanar with upper ends of the second conductive posts and the upper surface of the first mold layer;
• a passivation layer disposed on the first mold layer and the second mold layer;
• and a plurality of conductive connection structures passing through the passivation layer and respectively connected to the first and second conductive posts.