Microelectronic devices, related electronic systems, and methods of forming microelectronic devices

A microelectronic device, comprising:

• a first die comprising:
• a stack structure comprising alternating conductive structures and insulative structures intersecting vertical stacks of memory cells, horizontal edges of the alternating conductive structures and insulative structures defining steps of a staircase structure;
• and
• conductive contact structures in electrical communication with the conductive structures at the steps of the staircase structure;
• a second die vertically spaced from the first die, the second die comprising:
• an additional stack structure comprising alternating additional conductive structures and additional insulative structures intersecting additional vertical stacks of memory cells, horizontal edges of the alternating additional conductive structures and additional insulative structures defining steps of an additional staircase structure;
• and
• additional conductive contact structures in electrical communication with the additional conductive structures at the steps of the additional staircase structure;
• and
• a third die vertically between the first die and the second die, the third die comprising:
• first sub word line drivers in electrical communication with the conductive contact structures;
• and
• second sub word line drivers in electrical communication with the additional conductive contact structures and horizontally neighboring the first sub word line drivers in a horizontal direction.

A method of forming a microelectronic device, the method comprising:

• forming a first microelectronic device structure comprising:
• a memory array region comprising vertical stacks of memory cells;
• a stack structure intersecting the vertical stacks of memory cells and comprising conductive structures defining steps of a staircase structure;
• conductive contact structures individually in electrical communication with each step of the staircase structure;
• and
• a first oxide material overlying the memory array region;
• forming a second microelectronic device structure comprising:
• a first sub word line driver region;
• a second sub word line driver region;
• and
• a second oxide material overlying the first sub word line driver region and the second sub word line driver region;
• attaching the first microelectronic device structure to the second microelectronic device structure to form a microelectronic device structure assembly, attaching the first microelectronic device structure to the second microelectronic device structure comprising:
• horizontally aligning the conductive contact structures with circuitry of the first sub word line driver region;
• and
• bonding the first oxide material to the second oxide material;
• forming a third microelectronic device structure comprising:
• an additional memory array region comprising additional vertical stacks of memory cells;
• an additional stack structure intersecting the additional vertical stacks of memory cells and comprising additional conductive structures defining steps of an additional staircase structure;
• additional conductive contact structures individually in electrical communication with each step of the additional staircase structure;
• and
• a third oxide material overlying the additional memory array region;
• and
• attaching the third microelectronic device structure to the microelectronic device structure assembly, comprising:
• horizontally aligning the additional conductive contact structures with the second sub word line driver region;
• and
• bonding the third oxide material to a fourth oxide material of the microelectronic device structure assembly.

An electronic system, comprising:

• an input device;
• an output device;
• a processor device operably coupled to the input device and the output device;
• and
• a memory device operably coupled to the processor device and comprising:
• a first die comprising:
• a memory array region comprising vertical stacks of memory cells;
• conductive lines horizontally extending through the vertical stacks of memory cells, each conductive line of the conductive lines associated with a level of the memory cells of the vertical stacks of memory cells;
• conductive pillar structures vertically extending through the vertical stacks of memory cells, each conductive pillar structure of the conductive pillar structures vertically extending through access devices of the vertical stacks of memory cells;
• and
• conductive contact structures in electrical communication with the conductive lines;
• a second die attached to the first die, the second die comprising:
• a sub word line driver region comprising sub word line drivers in electrical communication with the conductive contact structures;
• and
• a third die attached to the second die opposite the first die, the third die comprising:
• an additional memory array region comprising additional vertical stacks of memory cells;
• additional conductive lines horizontally extending through the additional vertical stacks of memory cells, each additional conductive line of the additional conductive lines associated with a level of the memory cells of the additional vertical stacks of memory cells;
• and
• complementary metal-oxide semiconductor (CMOS) circuits farther from the second die than the additional memory array region.