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US 2023/0410935 A1Published application
Memory device and electronic device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChien-Yu Huang, Chia-En Huang, Cheng Hung Lee, Hua-Tai Shieh
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Abstract
Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.
Claims20
A method, comprising:
- providing a first column of memory cells, wherein a first local redundancy decoder circuit is operably connected to the first column of memory cells;
- providing a second column of memory cells immediately adjacent the first column of memory cells, wherein a second local redundancy decoder circuit is operably connected to the second column of memory cells, and wherein the first local redundancy decoder circuit differs from the second local redundancy decoder circuit;
- providing a third column of memory cells, wherein a separate first local redundancy decoder circuit is operably connected to the third column of memory cells;
- providing a fourth column of memory cells immediately adjacent the third column of memory cells, wherein a separate second local redundancy decoder circuit is operably connected to the fourth column of memory cells;
- determining the first column of memory cells is to be repaired;
- rippling a first output signal from the separate first local redundancy circuit operably connected to the third column of memory cells to a first input of the second local redundancy circuit operably connected to the second column of memory cells;
- rippling a second output signal from the first local redundancy circuit operably connected to the first column of memory cells to a second input of the second local redundancy circuit operably connected to the second column of memory cells;
- and
- using the first output signal received at the first input and the second output signal received at the second input in a decoding operation by the second local redundancy circuit operably connected to the second column of memory cells for repairing the first column of memory cells.
6 more elements
A method, comprising:
- providing a memory array comprising a plurality of memory cells arranged in rows and columns;
- providing a plurality of first local redundancy decoder circuits operably connected to a first subset of the columns in the memory array, wherein a respective one of the plurality of first local redundancy decoder circuits is operably connected to a respective one of every other column in the first subset;
- providing a plurality of second local redundancy decoder circuits operably connected to a second subset of the columns in the memory array, wherein a respective one of the plurality of second local redundancy decoder circuits is operably connected to a respective one of every other column in the second subset such that the first and the second local redundancy decoder circuits alternate between the columns;
- rippling a first output signal from at least one of the first local redundancy decoder circuits to an immediately preceding adjacent respective second local redundancy decoder circuit;
- rippling a second output signal from at least one of the first local redundancy decoder circuits to an immediately succeeding adjacent respective second local redundancy decoder circuit;
- and
- using the first and second output signals received by the second local redundancy decoder circuits for decoding operations.
4 more elements
A system, comprising:
- a decoder controller including an input terminal configured to receive an indication of a first column of memory cells is to be repaired;
- a first local redundancy decoder circuit connected to the decoder controller and to the first column of memory cells;
- a second local redundancy decoder circuit that differs from the first local redundancy decoder circuit, the second local redundancy controller connected to the decoder controller and to a second column of memory cells immediately adjacent the first column of memory cells;
- a separate first local redundancy decoder circuit connected the decoder controller and to a third column of memory cells;
- a separate second local redundancy decoder circuit connected to the decoder controller and to a fourth column of memory cells immediately adjacent the third column of memory cells;
- wherein the decoder controller is configured to:
- ripple a first output signal from the separate first local redundancy circuit operably connected to the third column of memory cells to a first input of the second local redundancy circuit operably connected to the second column of memory cells;
- and
- ripple a second output signal from the first local redundancy circuit operably connected to the first column of memory cells to a second input of the second local redundancy circuit operably connected to the second column of memory cells.
6 more elements
Dependencies are inferred from the claim text.